LTC1408 LINER [Linear Technology], LTC1408 Datasheet
LTC1408
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LTC1408 Summary of contents
Page 1
... QFN package. A SLEEP shutdown feature lowers power consumption to 6µW. The combina- tion of low power and tiny package makes the LTC1408 suitable for portable applications. The LTC1408 contains six separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal ...
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... Digital Input Voltage .................... – 0. Digital Output Voltage .................. – 0. Power Dissipation .............................................. 100mW Operation Temperature Range LTC1408C ............................................... 0°C to 70°C LTC1408I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 125° VERTER CHARACTERISTICS temperature range, otherwise specifications are at T PARAMETER ...
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... – 200µA DD OUT V = 2.7V 160µA DD OUT V = 2.7V 1.6mA DD OUT and V OUT 0V OUT OUT DD LTC1408 = V = 3V. CC MIN TYP MAX ● ● –80 –90 – – MIN TYP MAX 2 ...
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... LTC1408 W U POWER REQUIRE E TS range, otherwise specifications are at T SYMBOL PARAMETER Supply Voltage Supply Current Power Dissipation CHARACTERISTICS range, otherwise specifications are SYMBOL PARAMETER f Maximum Sampling Frequency per Channel SAMPLE(MAX) (Conversion Rate) t Minimum Sampling Period (Conversion + Acquisiton Period) ...
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... FREQUENCY(kHz) LTC1408 25° THD, 2nd and 3rd vs Input Frequency –44 BIPOLAR SINGLE ENDED – 1.5V CM –56 –62 –68 5 HARMONIC THD –74 3rd – ...
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... LTC1408 W U TYPICAL PERFOR A CE CHARACTERISTICS 610kHz Unipolar Single Ended Input Sine Wave 4096 Point FFT, 625ksps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 62.5 125 188 250 313 FREQUENCY(kHz) 1408 G10 Integral Linearity End Point Fit for CH0 with Internal 2 ...
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... DD – CH2 (Pin 11): Inverting Channel 2. CH2 – operates fully differentially with respect to CH2 ±1.25V differential swing and with a –2.5V to 0V, absolute input range. DD LTC1408 25° PSRR vs Frequency 0 –20 –40 –60 –80 100 1k ...
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... LTC1408 CTIO S + CH3 (Pin 14): Non-Inverting Channel 3. CH3 fully differentially with respect to CH3 or ±1.25V differential swing and input range. – CH3 (Pin 15): Inverting Channel 3. CH3 + differentially with respect to CH3 ±1.25V differential swing and input range. ...
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... LATCH 4 14-BIT LATCH 5 S & H TIMING LOGIC S & & H 2.5V REFERENCE V REF 10µF GND BIP SEL2 SEL1 SEL0 LTC1408 LTC1408 THREE- SD0 STATE 0.1µF SERIAL 1 OUTPUT OGND PORT 2 30 CONV 32 SCK 31 DGND 1408 BD 1408fa ...
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... LTC1408 DIAGRA S 10 1408fa ...
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... SCK CONV NAP SLEEP V REF NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK SDO Nap Mode and Sleep Mode Waveforms t 1 SCK to SDO Delay SCK SDO V OL LTC1408 1408 TD02 Hi-Z 1408 TD03 11 1408fa ...
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... During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1408 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used ...
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... If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1408 depends on the application. Generally, applications fall into two catego- ries: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical ...
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... Figure 1. RC Input Filter INPUT RANGE The analog inputs of the LTC1408 may be driven fully differentially with a single supply. Either input may swing 2.5V with BIP (Pin 29) Low, or ±1.25V with (BIP Pin 29) High. The 0V to 2.5V range is also ideally suited for single- ended input use with single supply applications ...
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... CMRR is typically better than –90dB Figure 4 shows the ideal input/output characteristics for the LTC1408 in unipolar mode (BIP = Low). The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is straight binary with 1LSB = 2.5V/16384 = 153µ ...
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... SCK wide to drive the LTC1408 and then buffer this signal to drive the frame sync input of the processor serial port good practice to drive the LTC1408 CONV input first to avoid digital noise interference during the sample-to- hold transition triggered by CONV at the start of conver- sion ...
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... CONV rises, the third rising edge of SCK sends out up to six sets of 14 data bits, with the MSB sent first. A simple approach is to generate SCK to drive the LTC1408 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port ...
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... V and CC DD time, at the full 600ksps conversion rate of the LTC1408. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1408 may be added to drive ...
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... UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 0.75 ± 0.05 0.00 – 0.05 3.45 ± 0.10 (4-SIDES) 0.200 REF LTC1408 BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP R = 0.115 OR 0.35 × 45° CHAMFER TYP 31 32 0.40 ± 0. (UH32) QFN 1004 0.25 ± ...
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... Initial Accuracy, 3ppm Drift 0.05% Initial Accuracy, 10ppm Drift NC7SVU04P5X 0.1µF MASTER CLOCK PRE CLR CONVERT ENABLE NL17SZ74 www.linear.com ● CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) TO LTC1408 CONV 1408 TA02 LT 0606 • PRINTED IN THE USA © LINEAR TECHNOLOGY CORPORATION 2006 1408fa ...