LTC2209 Linear Technology Corporation, LTC2209 Datasheet
LTC2209
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LTC2209 Summary of contents
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... ADC can be optimized with the PGA front end. P-P Input Range) P-P The LTC2209 is perfect for demanding communications applications, with AC performance that includes 77.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fs of high input frequencies with excellent noise performance. ...
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... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ................–0.3V to (OV Power Dissipation ............................................ 2500mW Operating Temperature Range LTC2209C ................................................ 0°C to 70°C LTC2209I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C Digital Output Supply Voltage (OV ORDER INFORMATION ...
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... Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) T 140MHz Input (1.5V Range, PGA = 1) 250MHz Input (2.25V Range, PGA = 0) 250MHz Input (1.5V Range, PGA = 1) LTC2209 MIN TYP 1.5 or 2.25 ● 1 1.25 ● ...
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... LTC2209 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER SFDR Spurious Free www.datasheet4u.com Dynamic Range th 4 Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio SFDR Spurious Free Dynamic Range at –25dBFS Dither “OFF” SFDR Spurious Free Dynamic Range at – ...
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... 3. –200µ 3. 1.60mA DD O 100Ω Differential Load 100Ω Differential Load 100Ω Differential Load 100Ω Differential Load LTC2209 MIN TYP MAX UNITS 1.15 1.25 1.35 V +40 ppm/° Ω MIN TYP MAX UNITS ● ...
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... LTC2209 POWER REQUIREMENTS range, otherwise specifi cations are at T SYMBOL PARAMETER V Analog Supply Voltage DD www.datasheet4u.com P Shutdown Power SHDN STANDARD LVDS OUTPUT MODE OV Output Supply Voltage DD I Analog Supply Current VDD I Output Supply Current OVDD P Power Dissipation DIS LOW POWER LVDS OUTPUT MODE ...
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... Note 7: Guaranteed by design, not subject to test. DD Note 8: Recommended operating conditions. without latchup P-P LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels – – – LTC2209 – – 3 2209 TD01 2209f 7 ...
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... LTC2209 TIMING DIAGRAMS www.datasheet4u.com ANALOG INPUT – ENC + ENC DA0-DA15, OFA CLKOUTA CLKOUTB DB0-DB15, OFB ANALOG INPUT – ENC + ENC DA0-DA15, OFA DB0-DB15, OFB CLKOUTA CLKOUTB 8 Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels ...
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... FREQUENCY (MHz) 2209 G07 LTC2209 AC Grounded Input Histogram 35000 28000 21000 14000 7000 0 49152 65536 32797 32807 OUTPUT CODE 2209 G02 64k Point FFT –20dBFS, PGA = 0, Dither “Off” ...
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... LTC2209 TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs Input Level 15MHz, IN www.datasheet4u.com PGA = 0, Dither “Off” 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 128k Point FFT 30.1MHz, IN –25dBFS, PGA = 0, Dither “On” ...
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... FREQUENCY (MHz) 2209 G25 LTC2209 64k Point 2-Tone FFT 70.25MHz and 74.3MHz, IN –15dBFS, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 ...
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... LTC2209 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT 250.1MHz, IN www.datasheet4u.com –10dBFS, PGA = 1, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) 64k Point FFT 380MHz, IN –10dBFS, PGA = 1 0 –10 –20 – ...
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... Mid-Scale Settling After Wake-Up from Shutdown or Starting Encode Clock 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 250 2.00 TIME AFTER WAKE-UP OR CLOCK START (µs) 2209 G40 LTC2209 Input Offset Voltage vs Temperature, 5 Units –1 –2 –3 –4 – –40 – TEMPERATURE (° ...
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... LTC2209 PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External www.datasheet4u.com Reference Input. Tie SENSE to V 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). ...
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... PGA (Pin 64): Programmable Gain Amplifi er Control Pin. Low selects a front-end gain of 1, input range of 2.25V selects a front-end gain of 1.5, input range of 1.5V GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be sol- dered to ground. LTC2209 – + /CLKOUT (Pins 39 and 40): LVDS Data Valid – ...
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... LTC2209 BLOCK DIAGRAM + A IN www.datasheet4u.com INPUT FIRST PIPELINED S/H ADC STAGE – DITHER SIGNAL GENERATOR RANGE SELECT SENSE V CM BUFFER VOLTAGE REFERENCE 16 SECOND PIPELINED THIRD PIPELINED ADC STAGE ADC STAGE ADC CLOCKS DIFFERENTIAL ADC INPUT PGA REFERENCE LOW JITTER CLOCK DRIVER + – ...
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... Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNR LTC2209 + equals the ENC π = –20log (2 • f • t ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2209 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (C through NMOS transistors. The capacitors shown attached to each input (C capacitance associated with each input ...
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... Transformer Coupled Circuits can be tied CM Figure 3 shows the LTC2209 being driven trans- former with a center-tapped secondary. The secondary center tap is DC biased with V signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50Ω ...
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... As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. 20 Reference Operation Figure 6 shows the LTC2209 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain ampli- fi er and control circuit. The LTC2209 has three modes ANALOG INPUT 2.2µF + 5Ω ...
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... SNR will be 1.8dB worse. See the typical performance curves section. Driving the Encode Inputs The noise performance of the LTC2209 can depend on the encode signal quality as much as for the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources ...
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... PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/ The lower limit of the LTC2209 sample rate is determined + ENC by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on – LTC2209 ENC small valued capacitors ...
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... Mode. DD TYPICAL Data Format DATA OUTPUT The LTC2209 parallel digital output can be selected for OGND offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level 2209 F11 logic input, centered at 0, 1/3V external resistor divider can be user to set the 1/3V and 2/3V for the MODE pin ...
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... LTC2209 APPLICATIONS INFORMATION Overfl ow Bit An overfl ow output bit (OF) indicates when the converter www.datasheet4u.com is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overfl underfl the A data bus, while a logic high on the OFB pin indicates an overfl ...
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... Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit Internal Dither FPGA The LTC2209 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfec- tions in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches ...
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... The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2209 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board critical that the exposed pad and all ground pins are connected to a ground plane of suffi ...
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... Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.75 ± 0. 0.10 TYP 7.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2209 R = 0.115 TYP 63 64 PIN 1 CHAMFER C = 0.35 7.15 ± 0.10 7.15 ± 0.10 (UP64) QFN 0406 REV C 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 27 0.40 ± 0.10 ...
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... LTC2209 RELATED PARTS PART NUMBER DESCRIPTION LTC1747 12-Bit, 80MSPS ADC www.datasheet4u.com LTC1748 14-Bit, 80Msps ADC LTC1749 12-Bit, 80Msps Wideband ADC LTC1750 14-Bit, 80Msps Wideband ADC LT1993 High Speed Differential Op Amp LTC2202 16-Bit, 10MSPS ADC LTC2203 16-Bit, 25MSPS ADC LTC2204 16-Bit, 40Msps ADC ...