w25q16bv Winbond Electronics Corp America, w25q16bv Datasheet
w25q16bv
Available stocks
Related parts for w25q16bv
w25q16bv Summary of contents
Page 1
... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: March 13, 2009 - 1 - Preliminary - Revision B W25Q16BV ...
Page 2
... Status Register Protect (SRP1, SRP0) 10.1.7 Erase Suspend Status (SUS) 10.1.8 Quad Enable (QE) 10.1.9 Status Register Memory Protection 10.2 INSTRUCTIONS 10.2.1 Manufacturer and Device Identification 10.2.2 Instruction Set Table 1 (Erase, Program Instructions) Table of Contents ............................................................................................................... 5 ................................................................................... 6 ........................................................................................ 6 ............................................................................................ 7 .................................................................................................. 7 ..................................................................................................................... 8 .................................................................................................................. 8 ............................................................................................................... 8 ..................................................................................................................... 8 ................................................................................................................ 8 ....................................................................................................... 10 ............................................................................................................. 10 .....................................................................................................10 ............................................................................................................10 ...........................................................................................................10 .......................................................................................................................10 ....................................................................................................... 11 ..........................................................................................................11 ........................................................................................ 12 .......................................................................................................... 12 ..................................................................................................12 ....................................................................................12 ...........................................................................................12 ................................................................................................12 ...............................................................................13 .............................................................................................13 ..............................................................................................................13 ....................................................................................15 ................................................................................................................. 16 .............................................................................. W25Q16BV ...................................................... 6 .................................... 8 ........................................................17 ...
Page 3
... Power-up Timing and Write Inhibit Threshold 11.4 DC Electrical Characteristics 11.5 AC Measurement Conditions 11.6 AC Electrical Characteristics 11.7 AC Electrical Characteristics (cont’d) 11.8 Serial Output Timing ........................................................................18 ..............................................................................................................20 .............................................................................................................20 ................................................................................................22 .................................................................................................................23 ...............................................................................................................24 ...........................................................................................25 ..........................................................................................26 .................................................................................................27 ...............................................................................................29 ..............................................................................................31 .....................................................................................33 .........................................................................................................35 ......................................................................................36 ...........................................................................................................37 ...................................................................................................38 ...................................................................................................39 .....................................................................................................40 ........................................................................................................41 ........................................................................................................41 ............................................................................................................42 ...........................................................................43 ...............................................................................45 .........................................................................................48 ......................................................................................................49 .............................................................................................. 51 ................................................................................................ 51 .............................................................................................................. 51 .................................................................... 52 .............................................................................................. 53 ............................................................................................. 54 .............................................................................................. 55 ................................................................................. 56 ........................................................................................................... W25Q16BV ...............................................................19 .......................................21 .................................................................46 ................................................................47 ................................................................50 Publication Release Date: March 13, 2009 Preliminary - Revision B ...
Page 4
... PACKAGE SPECIFICATION 12.1 8-Pin SOIC 150-mil (Package Code SN) 12.2 8-Pin SOIC 208-mil (Package Code SS) 12.3 8-Contact 6x5mm WSON (Package Code ZP) 12.4 16-Pin SOIC 300-mil (Package Code SF) 13. ORDERING INFORMATION 13.1 Valid Part Numbers and Top Side Marking 14. REVISION HISTORY ...................................................................................................................... 65 .......................................................................................................... 58 ........................................................................... 58 ........................................................................... 59 .................................................................. 60 .......................................................................... 62 .......................................................................................................... 63 ........................................................................ W25Q16BV ...
Page 5
... Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16BV has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
Page 6
... PIN CONFIGURATION SOIC 150 / 208-MIL Figure 1a. W25Q16BV Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q16BV Pad Assignments, 8-pad WSON 6x5-mm(Package Code ZP) 5. PIN DESCRIPTION SOIC 150/208-MIL, AND WSON 6X5-MM PIN NO. PIN NAME ...
Page 7
... PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q16BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N (IO1) 9 /WP (IO2) 10 GND 11 N/C 12 N/C 13 N (IO0) 16 CLK *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – ...
Page 8
... Package Types W25Q16BV is offered in an 8-pin plastic 150-mil or 208-mil width SOIC (package code SN & SS) and 6x5-mm WSON (package code ZP) as shown in figure 1a, and 1b, respectively. The W25Q16BV is also offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet. ...
Page 9
... SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q16BV Serial Flash Memory Block Diagram xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh ...
Page 10
... Hold Function The /HOLD signal allows the W25Q16BV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus ...
Page 11
... One Time Program (OTP) write protection Note 1: These features are available upon special order. Please refer to Ordering Information. Upon power- power-down, the W25Q16BV will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 32). While reset, all WI operations are disabled and no instructions are recognized ...
Page 12
... The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. , and Characteristics). When the program, erase or write status W25Q16BV ...
Page 13
... When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and can not be written to again (1) until the next power-down, power-up cycle. Status Register is permanently protected and can not be (1) written to. Publication Release Date: March 13, 2009 - 13 - W25Q16BV (2) Preliminary - Revision B ...
Page 14
... S2 S2 SEC SEC TB TB BP2 BP2 BP1 BP1 BP0 BP0 S15 S15 S14 S14 S13 S13 S12 S12 S11 S11 S10 S10 SUS SUS (R) (R) (R) (R) (R) (R) (R) (R) (R) ( W25Q16BV WEL BUSY WEL BUSY SRP1 SRP1 ...
Page 15
... X Note don’t care W25Q16BV (16M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 31 1F0000h – 1FFFFFh 30 and 31 1E0000h – 1FFFFFh 28 thru 31 1C0000h – 1FFFFFh 24 thru 31 180000h – 1FFFFFh 16 thru 31 100000h – 1FFFFFh 0 000000h – 00FFFFh 0 and 1 000000h – ...
Page 16
... INSTRUCTIONS The instruction set of the W25Q16BV consists of thirty basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
Page 17
... A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 A23–A16 A15–A8 FFh - 17 - W25Q16BV (1) BYTE 5 BYTE 6 A7–A0 (D7–D0) (3) A7–A0 (D7–D0, …) A7–A0 A7–A0 A7–A0 Publication Release Date: March 13, 2009 Preliminary - Revision B ...
Page 18
... The lowest 4 address bits must A0, A1, A2 BYTE 2 BYTE 3 A23-A16 A15-A8 A23-A16 A15-A8 A23-A16 A15-A8 (2) (2) A23-A8 A7-A0, M7-M0 A23-A16 A15-A8 (4) A23-A0, M7-M0 (x,x,x,x, D7-D0, …) (4) A23-A0, M7-M0 (x,x, D7-D0, …) (4) (3) A23-A0, M7-M0 (D7-D0, … W25Q16BV BYTE 4 BYTE 5 A7-A0 (D7-D0) A7-A0 dummy A7-A0 dummy (D7-D0, …) (1) (D7-D0, …) A7-A0 dummy (D7-D0, …) (5) (3) (D7-D0, …) (6) (3) (D7-D0, …) BYTE 6 (D7-D0) (1) (3) ...
Page 19
... See Manufacturer and Device Identification table for Device ID information. BYTE 2 BYTE 3 dummy dummy dummy dummy A23-A8 A7-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF7-MF0) (ID15-ID8) Manufacturer Memory Type dummy dummy - 19 - W25Q16BV BYTE 4 BYTE 5 BYTE 6 (1) dummy (ID7-ID0) 00h (MF7-MF0) (ID7-ID0) (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) (ID7-ID0) Capacity dummy dummy (ID63-ID0) Publication Release Date: March 13, 2009 ...
Page 20
... DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 4. Write Enable Instruction Sequence Diagram Figure 5. Write Disable Instruction Sequence Diagram - 20 - W25Q16BV ...
Page 21
... Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram Publication Release Date: March 13, 2009 - 21 - W25Q16BV Preliminary - Revision B ...
Page 22
... Write Protect (/WP) pin, Lock out or OTP features to disable writes to the status register. Please refer to 10.1.6 for detailed descriptions regarding Status Register protection methods. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram (See AC Characteristics W25Q16BV ...
Page 23
... Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram - 23 - W25Q16BV Publication Release Date: March 13, 2009 Preliminary - Revision B R ...
Page 24
... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram - 24 - W25Q16BV ...
Page 25
... The input data during the dummy clocks is “don’t care”. However, the IO out clock. Figure 10. Fast Read Dual Output Instruction Sequence Diagram and IO . This allows data to be transferred from the W25Q16BV pin should be high-impedance prior to the falling edge of the first data 0 ...
Page 26
... IO be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q16BV at four times the rate of standard SPI devices. ...
Page 27
... A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 10.2.33 for detailed descriptions). Figure 12a. Fast Read Dual I/O Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh) Publication Release Date: March 13, 2009 - 27 - W25Q16BV Preliminary - Revision B ...
Page 28
... Figure 12b. Fast Read Dual I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV ...
Page 29
... Figure 13a. Fast Read Quad I/O Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh The Quad I/O dramatically reduces instruction overhead . Publication Release Date: March 13, 2009 - 29 - W25Q16BV and IO and four Dummy 2 3 Byte 1 Byte 1 Byte 2 Byte 2 Preliminary - Revision B ...
Page 30
... Figure 13b. Fast Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV ...
Page 31
... Byte 2 Byte 2 Byte 1 Byte 1 Publication Release Date: March 13, 2009 - 31 - W25Q16BV ...
Page 32
... Figure 14b. Word Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh W25Q16BV ...
Page 33
... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Publication Release Date: March 13, 2009 - 33 - W25Q16BV ...
Page 34
... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte W25Q16BV ...
Page 35
... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 16. Page Program Instruction Sequence Diagram Publication Release Date: March 13, 2009 - 35 - W25Q16BV Preliminary - Revision B ...
Page 36
... All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 17. Figure 17. Quad Input Page Program Instruction Sequence Diagram , and IO . The Quad Page Program can W25Q16BV ...
Page 37
... Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 18. Sector Erase Instruction Sequence Diagram (See AC Characteristics). While the Sector Erase SE Publication Release Date: March 13, 2009 - 37 - W25Q16BV Preliminary - Revision B ...
Page 38
... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 19. 32KB Block Erase Instruction Sequence Diagram 1 (See AC Characteristics). While the Block Erase W25Q16BV ...
Page 39
... Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 20. 64KB Block Erase Instruction Sequence Diagram (See AC Characteristics). While the Block Erase cycle BE Publication Release Date: March 13, 2009 - 39 - W25Q16BV Preliminary - Revision B ...
Page 40
... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any section of the array is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Chip Erase cycle is in progress, CE Figure 21. Chip Erase Instruction Sequence Diagram - 40 - W25Q16BV ...
Page 41
... Erase Suspend. After issued the BUSY bit in the status register will be set and the sector or block will complete the erase operation. Resume instructions will be ignored unless an Erase Suspend operation is active. Figure 23. Erase Resume Instruction Sequence Diagram Publication Release Date: March 13, 2009 - 41 - W25Q16BV Preliminary - Revision B ...
Page 42
... This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 24. Deep Power-down Instruction Sequence Diagram - 42 - W25Q16BV ...
Page 43
... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 25b. The Device ID values for the W25Q16BV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. ...
Page 44
... Figure 25b. Release Power-down / Device ID Instruction Sequence Diagram - 44 - W25Q16BV ...
Page 45
... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 26. The Device ID values for the W25Q16BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
Page 46
... CLK with most significant bits (MSB) first as shown in figure 27. The Device ID values for the W25Q16BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other ...
Page 47
... ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. The Device ID values for the W25Q16BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
Page 48
... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q16BV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
Page 49
... Read JEDEC ID (9Fh) For compatibility reasons, the W25Q16BV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
Page 50
... If the system controller is Reset during operation it will likely send a standard SPI instruction, such as Read ID (9Fh) or Fast Read (0Bh), to the W25Q16BV. However, as with most SPI Serial Flash memories, the W25Q16BV does not have a hardware Reset pin Continuous Read Mode bits are set to “ ...
Page 51
... Electrostatic Discharge Voltage Notes: 1. Specification for W25Q16BV is preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. ...
Page 52
... Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t (1) VSL t (1) PUW V (1) WI Figure 32. Power-up Timing and Voltage Levels - 52 - W25Q16BV SPEC UNIT MAX µ ...
Page 53
... C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC –0.5 VCC –100 µA VCC – 0.2 OH Publication Release Date: March 13, 2009 - 53 - W25Q16BV SPEC UNIT TYP MAX ±2 µA ±2 µ µ µA 4/5/6 6/7.5/9 ...
Page 54
... Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL Figure 33. AC Measurement I/O Waveform - 54 - W25Q16BV SPEC UNIT MIN MAX 0.2 VCC to 0.8 VCC V 0.3 VCC to 0.7 VCC V 0.5 VCC to 0.5 VCC V ...
Page 55
... SHCH t t 7/40 SHSL CSH ( SHQZ DIS t t CLQV CLQV CLQX HO Publication Release Date: March 13, 2009 - 55 - W25Q16BV SPEC UNIT TYP MAX 80 MHz 104 MHz 50 MHz 50 MHz ns ns V/ns V/ 8 Continued – next page ...
Page 56
... SUS t W (4) t BP1 (4) t BP2 BPN BP1 + BP2 * W25Q16BV SPEC ALT MIN TYP 100 10 20 2.5 0.7 30 120 150 (typical) and = (max), where N = BPN BP1 + BP2 * N UNIT ...
Page 57
... Serial Output Timing 11.9 Input Timing 11.10 Hold Timing Publication Release Date: March 13, 2009 - 57 - W25Q16BV Preliminary - Revision B ...
Page 58
... Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. MILLIMETERS TYP. MAX MIN 1.60 1.72 0.058 --- 0.24 0.004 1.45 --- --- 0.41 0.50 0.013 0.20 0.25 0.0075 4.85 4.95 0.189 6.00 6.19 0.228 3.90 4.00 0.150 1.27 BSC 0.71 1.27 0.015 --- --- 0.10 --- - 58 - W25Q16BV INCHES TYP. MAX 0.063 0.068 --- 0.009 0.057 --- 0.016 0.020 0.008 0.0098 0.191 0.195 0.236 0.244 0.154 0.157 0.050 BSC 0.028 0.050 --- 8 o --- 0.004 ...
Page 59
... Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. MILLIMETERS INCHES MIN MAX MIN 1.75 2.16 0.069 0.05 0.25 0.002 1.70 1.91 0.067 0.35 0.48 0.014 0.19 0.25 0.007 5.18 5.38 0.204 7.70 8.10 0.303 5.18 5.38 0.204 1.27 BSC 0.050 BSC 0.50 0.80 0.020 --- 0.10 --- Publication Release Date: March 13, 2009 - 59 - W25Q16BV MAX 0.085 0.010 0.075 0.019 0.010 0.212 0.319 0.212 0.031 8 o 0.004 Preliminary - Revision B ...
Page 60
... MILLIMETERS MIN TYP. MAX 0.70 0.75 0.80 0.0276 0.00 0.02 0.05 0.0000 0.55 0.19 .0.20 0.25 0.0075 0.36 0.40 0.48 0.0138 5.90 6.00 6.10 0.2320 3.30 3.40 3.50 0.1299 4.90 5.00 5.10 0.1930 4.20 4.30 4.40 0.1653 1.27 BSC 0.20 0.0080 0.50 0.60 0.75 0.0197 - 60 - W25Q16BV INCHES MIN TYP. MAX 0.0295 0.0315 0.0008 0.0019 0.0126 0.0080 0.0098 0.0157 0.0190 0.2360 0.2400 0.1338 0.1377 0.1970 0.2010 0.1692 0.1732 0.0500 BSC 0.0236 0.0295 ...
Page 61
... The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. MILLIMETERS MIN TYP. MAX 3.40 4.30 6.00 0.50 0. W25Q16BV INCHES MIN TYP. MAX 0.1338 0.1692 0.2360 0.0196 0.0255 Publication Release Date: March 13, 2009 Preliminary - Revision B ...
Page 62
... Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. MILLIMETERS INCHES MIN MAX MIN 2.36 2.64 0.093 0.10 0.30 0.004 0.33 0.51 0.013 0.18 0.28 0.007 10.08 10.49 0.397 10.01 10.64 0.394 7.39 7.59 0.291 1.27 BSC 0.050 BSC 0.39 1.27 0.015 --- 0.076 --- - 62 - W25Q16BV MAX 0.104 0.012 0.020 0.011 0.413 0.419 0.299 0.050 8 o 0.003 ...
Page 63
... Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 2b. For shipments with OTP feature enabled, please specify when placing orders. (1) W 25Q 8-pad WSON 6x5mm SF = 16-pin SOIC 300-mil Publication Release Date: March 13, 2009 - 63 - W25Q16BV ( Preliminary - Revision B ...
Page 64
... Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q16BV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 11- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 9-digit number ...
Page 65
... Added Erase Suspend Status Bit 55, 63 & 64 Removed HPM instruction Updated max. read frequency Updated Ordering Information 63 Added note 2b. 5 Change Active Current to 4mA 13 Change QE pin to QE Bit Important Notice - 65 - W25Q16BV DESCRIPTION ranteed. Winbond Publication Release Date: March 13, 2009 Preliminary - Revision B ...