NUP4201DR2G ON Semiconductor, NUP4201DR2G Datasheet - Page 4

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NUP4201DR2G

Manufacturer Part Number
NUP4201DR2G
Description
IC TVS LO CAP HS DATA 500W 8SOIC
Manufacturer
ON Semiconductor
Datasheet

Specifications of NUP4201DR2G

Voltage - Reverse Standoff (typ)
5V
Voltage - Breakdown
6V
Power (watts)
500W
Polarization
4 Channel Array - Unidirectional
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Elements
8
Polarity
Uni-Directional
Package Type
SOIC
Operating Temperature Classification
Military
Reverse Breakdown Voltage
6V
Clamping Voltage
12V
Reverse Stand-off Voltage
5V
Leakage Current (max)
10uA
Peak Pulse Current
10A
Peak Pulse Power Dissipation
500W
Test Current (it)
1mA
Operating Temp Range
-55C to 150C
Mounting
Surface Mount
Pin Count
8
Operating Voltage
5 V
Breakdown Voltage
6 V
Termination Style
SMD/SMT
Peak Surge Current
10 A
Capacitance
5 pF
Maximum Operating Temperature
+ 150 C
Minimum Operating Temperature
- 55 C
Dimensions
4 (Max) mm W x 5 (Max) mm L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage voltage conditions. Because of its low
capacitance, it can be used in high speed I/O data lines. The
integrated design of the NUP4201DR2 offers surge rated,
low capacitance steering diodes and a TVS diode integrated
in a single package (SO−8). If a transient condition occurs,
the steering diodes will drive the transient to the positive rail
of the power supply or to ground. The TVS device protects
the power line against overvoltage conditions to avoid
damage to the power supply and any downstream
components.
NUP4201DR2 Configuration Options
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vcc+Vf). The
diodes will force the transient current to bypass the sensitive
circuit.
reference is connected at pins 5 and 8. These pins must be
connected directly to ground by using a ground plane to
minimize the PCB’s ground inductance. It is very important
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
Option 1
Vcc as reference.
positive supply rail (Vcc), the data lines are referenced to the
supply voltage. The internal TVS diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
The new NUP4201DR2 is a low capacitance TVS diode
The NUP4201DR2 is able to protect up to four data lines
Data lines are connected at pins 1, 4, 6 and 7. The negative
Protection of four data lines and the power supply using
For this configuration, connect pins 2 and 3 directly to the
I/O 1
I/O 2
I/O 3
I/O 4
V
CC
1
2
3
4
Figure 5.
8
7
6
5
APPLICATIONS INFORMATION
http://onsemi.com
4
Option 2
isolation resistor.
by connecting a series resistor between pins 2 and 3 and Vcc.
A 10 kW resistor is recommended for this application. This
will maintain a bias on the internal TVS and steering diodes,
reducing their capacitance.
Option 3
as reference.
those cases in which a fully isolated power supply is
required, the internal TVS can be used as the reference. For
these applications, pins 2 and 3 are not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the TVS plus one diode drop (Vc=Vf + V
ESD Protection of Power Supply Lines
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
Protection of four data lines with bias and power supply
The NUP4201DR2 can be isolated from the power supply
Protection of four data lines using the internal TVS diode
In applications lacking a positive supply reference or
When using diodes for data line protection, referencing to
10 K
I/O 1
I/O 2
I/O 3
I/O 4
I/O 1
I/O 2
I/O 3
I/O 4
V
CC
NC
NC
1
2
3
4
1
2
3
4
Figure 6.
Figure 7.
8
7
6
5
8
7
6
5
TVS
).

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