PIC16F716-I/SO Microchip Technology, PIC16F716-I/SO Datasheet - Page 155

• Manufacturer Part Number: PIC16F716-I/SO
• Description: IC PIC MCU FLASH 2KX14 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F716-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 8-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3-DB16F716 - BOARD DAUGHTER ICEPIC3AC162054 - HEADER INTERFACE ICD2 16F716AC164010 - MODULE SKT PROMATEII DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.10.2
1997 Microchip Technology Inc.
Note:
PIC16CXXX
Successive Operations on an I/O Port
This is not a capacitor to ground, but the effective capac-
itive loading on the trace.
I/O
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading,
the data must be valid at the beginning of the instruction cycle
must be exercised if a write followed by a read operation is carried out on the same I/O port. The
sequence of instructions should be such to allow the pin voltage to stabilize (load dependent)
before the next instruction which causes that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU rather than the new state. When in doubt,
it is better to separate these instructions with a NOP or another instruction not accessing this I/O
port.
Figure 9-12: Successive I/O Operation
Figure 9-13
becomes larger, the rise/fall time of the I/O pin increases. As the device frequency increases or
the effective capacitance increases, the possibility of this subsequent PORTx read-modify-write
instruction issue increases. This effective capacitance includes the effects of the board traces.
The best way to address this is to add an series resistor at the I/O pin. This resistor allows the
I/O pin to get to the desired level before the next instruction.
The use of NOP instructions between the subsequent PORTx read-modify-write instructions, is a
lower cost solution, but has the issue that the number of NOP instructions is dependent on the
effective capacitance C and the frequency of the device.
Figure 9-13: I/O Connection Issues
This example shows a write to PORTB followed by a read from PORTB.
Instruction
Instruction
Note:
RB7:RB0
executed
C
fetched
(1)
shows the I/O model which causes this situation. As the effective capacitance (C)
PORTx, PINy
PC
Data setup time = (0.25T
whereT
T
Therefore, at higher clock frequencies, a write followed by a read may be
problematic due to external capacitance.
PD
Q1
MOVWF PORTB
= propagation delay
write to
PORTB
CY
Q2
PC
V
IL
= instruction cycle
Q3 Q4
BSF PORTx, PINy
Q2
MOVF PORTB,W
MOVWF PORTB
Q1
Q3
write to
PORTB
CY
Q2
PC + 1
Section 9. I/O Ports
- T
Q4
Q3 Q4
PD
Read PORTx, PINy as low
)
BSF PORTx, PINz clears the value
to be driven on the PORTx, PINy pin.
Q1
T
Q1
MOVF PORTB,W
PD
BSF PORTx, PINz
Port pin
sampled here
Q2
NOP
PC + 2
Q2
Q3 Q4
(Figure
Q3
9-12). Therefore, care
Q1
DS31009A-page 9-15
Q4
Q2
PC + 3
NOP
NOP
Q3 Q4
Q1
9