PIC16F688-I/SL Microchip Technology, PIC16F688-I/SL Datasheet - Page 2

• Manufacturer Part Number: PIC16F688-I/SL
• Description: IC PIC MCU FLASH 4KX14 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/SL

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
7. Module: EUSART – TX Pin Tri-states
8. Module: EUSART – TX Pin Tri-states After
9. Module: EUSART – Auto-Baud Always
10. Module: Resets (when WDT times out)
DS80181G-page 2
When TXEN is clear, the TX pin will automatically
be tri-stated. Note that the TXEN bit is cleared after
an auto-baud overflow condition.
Work around
None.
The TX pin will briefly tri-state for approximately
8 bit times after an auto-baud completes, regard-
less of setting of TXEN.
Work around
None.
The EUSART auto-baud feature requires 5 edges
on the RC pin to complete the auto-baud process.
If the auto-baud timer overflows, the EUSART will
still require a total of 5 edges before completing
the auto-baud. While an auto-baud is in progress,
the RCIDL bit will remain active indicating that a
receive is in progress. If an overflow occurs, it will
require the reception of a second character to
complete the auto-baud process. When the auto-
baud process completes, the BRGH register will
be updated and the RCIDL bit will clear. If an auto-
baud overflow occurred, the new BRGH value
generated during the second received character
will be invalid.
Work around
When an auto-baud overflow occurs, the EUSART
cannot be completely reset until a second charac-
ter is received. Once the second character has
arrived, the EUSART can be reset and normal
operation can resume, regardless of SPEN.
If the OPTION_REG bits, PS<2:0>, are clear,
multiple spurious Resets can occur when the WDT
times out. These Resets can occur even when the
PSA bit is clear, assigning the prescaler to the
Timer0.
Work around
If a CLRWDT instruction is issued before the WDT
times out and before the OPTION register is
modified, this problem is eliminated.
Date Codes that pertain to this issue:
All Rev. A3 silicon PIC16F688 devices.
When TXEN is Clear
Auto-baud
Completes After 5 Edges on RC
Pin
11. Module: Data EEPROM Memory
12. Module: EUSART
BRG16 = 0
BRG16 = 1
The EEIF flag may be cleared inadvertently when
performing operations on the PIR1 register simul-
taneously with the completion of an EEPROM
write. This condition occurs when the EEPROM
write timer completes at the same moment that the
PIR1 register operation is executed. Register
operations are those that have the PIR1 register
as the destination and include, but are not limited
to, BSF, BCF, ANDWF, IORWF and XORWF.
Work arounds
1. Avoid operations on the PIR1 register when
2. Poll the WR bit (EECON1<1>) to determine
3. Use a timer interrupt to catch any instances
4. If periodic interrupts are occurring in addition to
When BRG16 and BRGH are both set, the first
edge of the received Start bit is not measured
accurately. This will cause the sampling position
for each bit to be up to 25% late. Multiple bytes
received back-to-back will see a compounding
error and some data could be lost.
Work around
Do not configure the EUSART with BRG16 and
BRGH = 1.
writing to the EEPROM memory.
when the write is complete.
when the EEIF flag is inadvertently cleared.
The timer interrupt should be set longer than
8 ms. If EEIF fails, then the timer interrupt
occurs as a default time out. The WR and
WRERR flags are checked as part of the timer
Interrupt
EEPROM write success.
the EEIF interrupts, then use a secondary flag
to sense write completion. The secondary flag
is set whenever EEPROM writes are active. An
EEPROM write completion is indicated when
the secondary flag is set and the WR flag is
clear.
Service
BRGH = 0
Good
Good
© 2008 Microchip Technology Inc.
Routine
Not Recommended
BRGH = 1
to
Good
verify
the