PIC16F688-I/SL Microchip Technology, PIC16F688-I/SL Datasheet
PIC16F688-I/SL
Specifications of PIC16F688-I/SL
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PIC16F688-I/SL Summary of contents
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... Microchip Technology Inc. PIC16F688 Data Sheet 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology Preliminary DS41203B ...
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... ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. ...
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... Flash/Data EEPROM retention: > 40 years Program Memory Device Flash (words) PIC16F688 4096 2004 Microchip Technology Inc. PIC16F688 Low-Power Features • Standby Current 2.0V, typical • Operating Current kHz, 2.0V, typical - 100 MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical Peripheral Features • ...
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... PIC16F688 Pin Diagram 14-pin PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/RX/DT RC4/C2OUT/TX/CK RC3/AN7 DS41203B-page RA0/AN0/C1IN+/ICSPDAT/ULPWU 13 RA1/AN1/C1IN-/ RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN RC1/AN5/C2IN RC2/AN6 7 8 Preliminary /ICSPCLK REF 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. Preliminary PIC16F688 DS41203B-page 3 ...
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... PIC16F688 NOTES: DS41203B-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... The PIC16F688 is covered by this data sheet available in 14-pin PDIP, SOIC and TSSOP packages. Figure 1-1 shows a block diagram of the PIC16F688 device. Table 1-1 shows the pinout description. ...
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... PIC16F688 TABLE 1-1: PIC16F688 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C1IN-/V /ICSPCLK RA1 REF AN1 C1IN- V ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 ...
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... Program Memory Organization The PIC16F688 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-01FFF) for the PIC16F688 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
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... PIC16F688 FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA 06h PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh ...
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... TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s register 02h PCL Program Counter's (PC) Least Significant Byte 03h STATUS ...
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... PIC16F688 TABLE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter's (PC) Least Significant Byte 83h STATUS ...
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... TABLE 2-3: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module’s register 102h PCL Program Counter's (PC) Least Significant Byte 103h STATUS ...
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... PIC16F688 TABLE 2-4: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 181h OPTION_REG RAPU INTEDG 182h PCL Program Counter's (PC) Least Significant Byte 183h STATUS ...
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... Status bits. For other instructions not affecting any Status bits (see Section 12.0 “Instruction Set Sum- mary”). Note 1: Bits IRP and RP1 (Status<7:6>) are not used by the PIC16F688 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. ...
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... PIC16F688 2.2.2.2 Option Register The Option register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External RA2/INT interrupt • TMR0 • Weak pull-ups on PORTA REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h) R/W-1 ...
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... R/W-0 R/W-0 R/W-0 R/W-0 T0IE INTE RAIE T0IF (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R/W-0 R/W-0 INTF RAIF bit Bit is unknown DS41203B-page 15 ...
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... PIC16F688 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt ...
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... R-0 R/W-0 R/W-0 R/W-0 RCIF C2IF C1IF OSFIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R-0 R/W-0 TXIF TMR1IF bit Bit is unknown DS41203B-page 17 ...
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... PIC16F688 2.2.2.6 PCON Register The Power Control (PCON) register (See Table 12-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD ...
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... Microchip Technology Inc. 2.3.2 STACK The PIC16F688 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (Status<7>), as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F688 Direct Addressing From Opcode RP1 RP0 6 ...
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... Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz 2004 Microchip Technology Inc. The PIC16F688 can be configured in one of eight clock modes – External clock with I/O on RA4 – Low gain Crystal or Ceramic Resonator Oscillator mode – Medium gain Crystal or Ceramic Resona- tor Oscillator mode ...
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... External Clock Modes 3.3.1 OSCILLATOR START-UP TIMER (OST) If the PIC16F688 is configured for LP modes, the Oscillator Start-up Timer (OST) counts 1024 oscil- lations from the OSC1 pin, following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended ...
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... additional parallel feedback resistor (R may be required for proper ceramic resonator operation (typical value Internal Logic Sleep to vary Preliminary PIC16F688 CERAMIC RESONATOR OPERATION ( MODE) PIC16F688 OSC1 To Internal Logic P (3) Sleep ( OSC2 S ( may be required for S varies with the oscillator ...
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... The user also needs to take into account variation due to tolerance of external RC components used. DS41203B-page 24 3.4 Internal Clock Modes The PIC16F688 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ± ...
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... Monitor (FSCM), and peripherals, are not affected by the change in frequency. U-0 U-0 R/W-0 R/W-0 — — TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown DS41203B-page 25 ...
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... PIC16F688 3.4.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The ...
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... OSTS bit (OSCCON<3>) to remain clear. 2004 Microchip Technology Inc. When the PIC16F688 is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 (OST)”). The OST timer will suspend program ...
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... PIC16F688 FIGURE 3-7: TWO-SPEED START- INTOSC T T OST OSC1 0 1 1022 1023 OSC2 Program Counter System Clock 3.7 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator ...
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... The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC16F688 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. ...
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... PIC16F688 REGISTER 3-2: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh) U-0 R/W-1 — IRCF2 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz ...
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... MOVLW 0Ch MOVWF TRISA BCF STATUS,RP0 4.2 Additional Pin Functions Every PORTA pin on the PIC16F688 has an interrupt- on-change option and a weak pull-up option. PORTA also provides an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 WEAK PULL-UPS Each of the PORTA pins, except RA3, has an individu- ally configurable internal weak pull-up ...
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... PIC16F688 REGISTER 4-2: TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h OR 185h) U-0 — bit 7 bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISA<5:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output Note 1: TRISA<3> always reads ‘1’. ...
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... U-0 R/W-0 R/W-0 R/W-0 — IOCA5 IOCA4 IOCA3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R/W-0 R/W-0 R/W-0 IOCA2 IOCA1 IOCA0 bit Bit is unknown DS41203B-page 33 ...
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... PIC16F688 4.2.3 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt- on-change on RA0 without excess current consump- tion. The mode is selected by setting the ULPWUE bit (PCON<5>). This enables a small current sink which can be used to discharge a capacitor on RA0. ...
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... IOCA Interrupt-on- Change To Comparator To A/D Converter Note 1: Comparator mode and ANSEL determines analog input mode. 2004 Microchip Technology Inc. (1) Analog Input Mode V DD Weak RAPU - + ULP 0 1 (1) Analog Vss Input Mode ULPWUE PORTA Preliminary PIC16F688 V DD I/O PIN V SS DS41203B-page 35 ...
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... PIC16F688 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet. ...
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... Master Clear Reset with weak pull-up FIGURE 4-4: Data Bus Weak TRISA RD PORTA IOCA DD RD IOCA I/O pin Interrupt-on- change Preliminary PIC16F688 PP BLOCK DIAGRAM OF RA3 V DD MCLRE Weak MCLRE Reset Input pin V SS MCLRE PORTA DS41203B-page 37 ...
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... PIC16F688 4.2.4.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • a TMR1 gate input • a crystal/resonator connection • a clock output FIGURE 4-5: ...
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... ANS5 ANS4 ANS3 ANS2 ANS1 WPUA5 WPUA4 — WPUA2 WPUA1 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 Preliminary PIC16F688 Value on: Value on all Bit 0 POR, BOD other Resets RA0 --xx xx00 --uu uu00 RAIF 0000 0000 0000 0000 CM0 0000 0000 0000 0000 PS0 1111 1111 ...
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... PIC16F688 4.3 PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter or compara- tor. For specific information about individual functions such as the EUSART or the A/D, refer to the appropriate section in this data sheet ...
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... I/O for the EUSART FIGURE 4-9: USART Select C2OUT EN EUSART TX/CLKOUT Data Bus C2OUT PORTC I/O Pin TRISC SS RD TRISC RD PORTC To EUSART CLK Input Note 1: USART Select signals selects between port data and peripheral output. Preliminary PIC16F688 BLOCK DIAGRAM OF RC4 ( I/O Pin V SS DS41203B-page 41 ...
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... PIC16F688 4.3.6 RC5/RX/DT The RC5 is configurable to function as one of the following: • a general purpose I/O • a digital I/O for the EUSART FIGURE 4-10: BLOCK DIAGRAM OF RC5 PIN Data Bus EUSART Out Enable EUSART 1 PORTC DT Out TRISC RD TRISC RD PORTC To EUSART RX/DT In DS41203B-page I/O Pin ...
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... Bit 1 RC5 RC4 RC3 RC2 C2INV C1INV CIS CM2 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 ANS5 ANS4 ANS3 ANS2 ANS1 Preliminary PIC16F688 R/W-x R/W-0 R/W-0 RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown ...
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... PIC16F688 NOTES: DS41203B-page 44 Preliminary 2004 Microchip Technology Inc. ...
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... Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep, since the timer is shut off during Sleep. 8-bit Prescaler PSA 8 PS<2:0> 16-bit 16 PSA WDTPS<3:0> Preliminary PIC16F688 edge (T0SE) control ® Mid-Range MCU Family Data Bus 8 1 SYNC 2 TMR0 Cycles ...
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... Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F688. See Section 11.7 “Watchdog Timer (WDT)” for more information. Legend Readable bit - n = Value at POR DS41203B-page 46 (and OSC OSC ...
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... Bit 1 T0IE INTE RAIE T0IF INTF T0CS T0SE PSA PS2 PS1 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Preliminary PIC16F688 CHANGING PRESCALER (TIMER0 WDT) ;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ...
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... PIC16F688 NOTES: DS41203B-page 48 Preliminary 2004 Microchip Technology Inc. ...
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... TIMER1 MODULE WITH GATE CONTROL The PIC16F688 has a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • ...
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... PIC16F688 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit timer with prescaler • 16-bit synchronous counter • 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruc- tion cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In ...
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... R = Readable bit - n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) (2) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS41203B-page 51 ...
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... PIC16F688 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow, which will wake-up the processor ...
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... Figure 7-3. ) REF R-0 R/W-0 R/W-0 R/W-0 C2INV C1INV CIS - Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R/W-0 R/W-0 R/W-0 CM2 CM1 CM0 bit Bit is unknown DS41203B-page 53 ...
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... PIC16F688 7.1 Comparator Operation A single comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... FIGURE 7-2: ANALOG INPUT MODEL Rs < 10K PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage 2004 Microchip Technology Inc 0. Leakage V = 0.6V T ±500 nA Vss Preliminary PIC16F688 DS41203B-page 55 ...
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... PIC16F688 7.3 Comparator Configuration There are eight modes of operation for the comparators. The CMCON0 register is used to select these modes. Figure 7-3 shows the eight possible modes. FIGURE 7-3: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) CM<2:0> = 000 RA1/AN1 Off ...
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... COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2SYNC To TMR1 To C2OUT pin To Data Bus RD CMCON Set C2IF bit Note 1: Comparator 2 output is latched on falling edge of T1 clock source. 2004 Microchip Technology Inc NReset TMR1 EN clock source Reset Preliminary PIC16F688 C1INV Q3 RD CMCON C2INV ( CMCON DS41203B-page 57 ...
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... PIC16F688 REGISTER 7-2: CMCON1 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 1Ah) U-0 — bit 7 bit 7-2: Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G pin (RA4 must be configured as digital input Timer1 gate source is Comparator 2 Output ...
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... V REF tested absolute accuracy of the comparator voltage reference can be found in Section 14.0 “Electrical Specifications”. DD /32 Stages Preliminary PIC16F688 to V cannot be realized due from approaching V or REF SS when VR<3:0> = 0000. SS module current. REF derived and therefore, the DD ...
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... PIC16F688 7.7 Comparator Response Time Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 14-9) ...
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... T1GSS TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 RCIE C2IE C1IE OSFIE VRR — VR3 VR2 Preliminary PIC16F688 R/W-0 R/W-0 R/W-0 VR2 VR1 VR0 bit REF Bit is unknown Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF ...
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... PIC16F688 NOTES: DS41203B-page 62 Preliminary 2004 Microchip Technology Inc. ...
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... The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either voltage applied by the V DD shows the block diagram of the A/D on the PIC16F688 VCFG = 0 V REF VCFG = 1 ...
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... PIC16F688 8.1.4 CONVERSION CLOCK The A/D conversion cycle requires the conversion clock is software selectable via the ADCS bits (ADCON1<6:4>). There are seven possible clock options: • OSC • OSC • OSC • F /16 OSC • F /32 OSC • F /64 OSC • F ...
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... A/D Result MSB bit 0 bit 7 R/W-1 R/W-1 R/W-1 ANS5 ANS4 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 ADRESL LSB bit 0 Unimplemented: Read as ‘0’ LSB bit 0 10-bit A/D Result ...
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... PIC16F688 REGISTER 8-2: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 ADFM VCFG bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit pin REF bit 5 Unimplemented: Read as ‘0’ bit 4-2 CHS<2:0>: Analog Channel Select bits ...
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... MOVF ADRESH,W MOVWF RESULTHI BSF STATUS,RP0 MOVF ADRESL,W MOVWF RESULTLO is AD Preliminary PIC16F688 A/D CONVERSION ;Bank 1 ;A/D RC clock ;Set RA0 to input ;Set RA0 to analog ;Bank 0 ;Right, Vdd Vref, AN0 ;Wait min sample time ;Start conversion ;Is conversion done? ;No, test again ;Read upper 2 bits ...
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... PIC16F688 8.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-4. The source impedance (R ) and the internal sampling switch (R ...
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... RC, a SLEEP instruction causes the present conversion to be aborted, and the A/D module is turned off. The ADON bit remains set. Full-Scale Range 1 LSB Ideal 1/2 LSB Ideal Full-Scale Transition 1/2 LSB Ideal Zero-Scale Transition Preliminary PIC16F688 Center of Full-Scale Code Analog Input DS41203B-page 69 ...
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... PIC16F688 8.4 Effects of Reset A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged. TABLE 8-2: SUMMARY OF A/D REGISTERS Addr Name Bit 7 Bit 6 05h/ PORTA — — ...
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... EEDAT and EEADR registers. Interrupt flag bit EEIF (PIR1<7>), is set when write is complete. It must be cleared in the software. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. Preliminary PIC16F688 DS41203B-page 71 ...
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... PIC16F688 REGISTER 9-1: EEDAT – EEPROM DATA REGISTER (ADDRESS: 9Ah) R/W-0 R/W-0 EEDAT7 EEDAT6 bit 7 bit 7-0 EEDATn: Byte Value to Write to or Read From Data EEPROM bits Legend Readable bit - n = Value at POR REGISTER 9-2: EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh) ...
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... WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. Preliminary PIC16F688 DS41203B-page 73 ...
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... PIC16F688 9.1.4 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control (EECON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data ...
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... RCIF C2IF C1IF OSFIF RCIE C2IE C1IE OSFIE — — WRERR WREN — — — — Preliminary PIC16F688 PC+4 PC+5 INSTR (PC+3) INSTR (PC+4) INSTR(PC+3) INSTR(PC+4) executed here executed here Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF RAIF ...
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... PIC16F688 NOTES: DS41203B-page 76 Preliminary 2004 Microchip Technology Inc. ...
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... ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is the serial I/O module available for PIC16F688 . (EUSART is also known as a Serial Communications Interface or SCI). The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers ...
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... PIC16F688 REGISTER 10-1: TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 16h) R/W-0 R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode Master mode (clock generated internally from BRG Slave mode (clock from external source) ...
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... Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown DS41203B-page 79 ...
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... PIC16F688 REGISTER 10-3: BAUDCTL – BAUD RATE CONTROL REGISTER (ADDRESS: 11h) R-0 ABDOVF RCIDL bit 7 bit 7 ABDOVF: Auto Baud Detect Overflow bit Asynchronous mode Auto baud timer overflowed 0 = Auto baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive IDLE Flag bit ...
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... Solving for SPBRGH:SPBRG: , the nearest Calculated Baud Rate Error Note: When BRGH = 1 and BRG16 = 1 then SPBRGH:SPBRG values BRG/USART Mode 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous Preliminary PIC16F688 CALCULATING BAUD RATE ERROR of 16 MHz, desired baud rate OSC -------------------------------------------------------------------- - = 64 [SPBRGH:SPBRG -------------------------------------------- - Desired Baud Rate ...
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... PIC16F688 TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Addr Name Bit 7 Bit 6 11h BAUDCTL ABDOVF RCIDL 12h SPBRGH 13h SPBRG 16h TXSTA CSRC TX9 17h RCSTA SPEN RX9 Legend unknown unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. ...
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... Preliminary PIC16F688 SPBRG % value (decimal) 207 51 25 — — — — SPBRG % value (decimal) 1665 415 207 — SPBRG % ...
Page 86
... PIC16F688 TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD F = 4.000 MHz OSC RATE Actual SPBRG Actual (K) % Rate value Error (K) (decimal) 0.3 0.300 0.01 3332 1.2 1.200 0.04 832 2.4 2.404 0.16 415 9.6 9.615 ...
Page 87
... The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0. 2004 Microchip Technology Inc. Edge #1 Edge #2 Edge #3 Bit 1 Bit 3 Start Bit 0 Bit 2 Bit 4 XXXXh XXXXh Preliminary PIC16F688 001Ch Edge #5 Edge #4 Bit 5 Bit 7 Bit 6 Stop Bit Auto Cleared 1Ch 00h DS41203B-page 85 ...
Page 88
... PIC16F688 10.3 USART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the USART uses standard non-return-to-zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip ...
Page 89
... TXREG Register 8 LSb (8) 0 TSR Register TRMT TX9 TX9D bit 0 bit 1 Word 1 bit 0 bit 1 Word Preliminary PIC16F688 RC4/C2OUT/TX/CK pin Pin Buffer and Control SPEN bit 7/8 Stop bit Start bit bit 7/8 bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. DS41203B-page 87 ...
Page 90
... PIC16F688 TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Addr Name Bit 7 Bit 6 0Ch PIR1 EEIF ADIF 11h BAUDCTL ABDOVF RCIDL 12h SPBRGH USART Baud Rate High Generator 13h SPBRG USART Baud Rate Generator 14h RCREG USART Receive Register 15h TXREG USART Transmit Register ...
Page 91
... ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. CREN OERR 64 RSR Register MSb or 16 Stop ( RX9 Data Recovery RX9D RCREG Register Interrupt RCIF RCIE Preliminary PIC16F688 FERR RCIDL LSb 1 0 START FIFO 8 Data Bus DS41203B-page 89 ...
Page 92
... PIC16F688 FIGURE 10-6: ASYNCHRONOUS RECEPTION Start bit RX (pin) bit 0 bit 1 Rcv Shift Reg Rcv Buffer Reg RCIDL Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set ...
Page 93
... Clear all interrupt flags including RCIF. 2. Check RCIDL to ensure no receive is currently in progress characters are being received so the WUE bit can be set. 4. Sleep. Cleared due to User Read of RCREG Q1Q2 Q3 Q4 Cleared due to User Read of RCREG Sleep Ends Preliminary PIC16F688 Auto Cleared Auto Cleared DS41203B-page 91 ...
Page 94
... PIC16F688 10.3.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTA< ...
Page 95
... TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 bit 2 bit 7 bit 0 bit 1 Word 2 Preliminary PIC16F688 ), the TXREG is empty CYCLE bit 7 ‘1’ DS41203B-page 93 ...
Page 96
... PIC16F688 FIGURE 10-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC5/RX/DT pin RC4/C2OUT/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit TABLE 10-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Addr Name Bit 7 Bit 6 0Ch PIR1 EEIF ADIF 11h BAUDCTL ABDOVF RCIDL 12h ...
Page 97
... RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. bit 1 bit 2 bit 3 bit 4 Preliminary PIC16F688 Q1Q2Q3Q4 bit 5 bit 6 bit 7 ‘0’ DS41203B-page 95 ...
Page 98
... PIC16F688 TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Addr Name Bit 7 Bit 6 0Ch PIR1 EEIF ADIF 11h BAUDCTL ABDOVF RCIDL 12h SPBRGH USART Baud Rate High Generator 13h SPBRG USART Baud Rate Generator 14h RCREG USART Receive Register 15h TXREG ...
Page 99
... TXEN SYNC SENDB BRGH TRMT SREN CREN ADDEN FERR OERR RCIE C2IE C1IE OSFIE TXIE Preliminary PIC16F688 Value on Value on Bit 0 all other POR, BOD Resets TMR1IF 0000 0000 0000 0000 ABDEN 00-0 0-00 00-0 0-00 0000 0000 0000 0000 0000 0000 ...
Page 100
... PIC16F688 10.5.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any IDLE mode and bit SREN, which is a “don't care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep, then a word may be received. Once the word is received, the RSR register will transfer the data to the RCREG register ...
Page 101
... SPECIAL FEATURES OF THE CPU The PIC16F688 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD) • ...
Page 102
... PIC16F688 11.1 Configuration Bits The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 11-1. These bits are mapped in program memory location 2007h. REGISTER 11-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) — ...
Page 103
... Programming it is not FCAL2 FCAL1 FCAL0 — POR1 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F688 memory space (2000h- Programming Specification” POR0 BOD2 BOD1 BOD0 bit Bit is unknown DS41203B-page 101 ...
Page 104
... PIC16F688 11.3 Reset The PIC16F688 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Detect (BOD) Some registers are not affected in any Reset condition; ...
Page 105
... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 11.4.1 MCLR PIC16F688 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
Page 106
... BOD 64 ms Reset. (Section 14.0 11.4.5 BOD CALIBRATION The PIC16F688 stores the BOD calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the speci- fied bulk erase sequence in the PIC12F6XX/16F6XX Memory Programming Specification (DS41204) and thus, does not require reprogramming ...
Page 107
... Then, bringing MCLR high will begin execution immediately (see Figure 11-5). This is useful for testing purposes or to synchronize more than one PIC16F688 device operating in parallel. Table 11-5 shows the Reset conditions for some special registers, while Table 11-4 shows the Reset conditions for all the registers ...
Page 108
... PIC16F688 FIGURE 11-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR ...
Page 109
... Preliminary PIC16F688 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu ...
Page 110
... PIC16F688 TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Power-on Register Address Reset OSCCON 8Fh -110 x000 OSCTUNE 90h ---0 0000 ANSEL 91h 1111 1111 WPUA 95h --11 -111 IOCA 96h --00 0000 EEDATH 97h --00 0000 EEADRH 98h ---- 0000 VRCON 99h 0-0- 0000 EEDAT 9Ah ...
Page 111
... Interrupts The PIC16F688 has 11 sources of interrupt: • External Interrupt RA2/INT • TMR0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt The Interrupt Control (INTCON) register and Peripheral Interrupt Request 1 (PIR1) register record individual interrupt requests in flag bits ...
Page 112
... PIC16F688 11.5.1 RA2/INT INTERRUPT External interrupt on RA2/INT pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt ...
Page 113
... Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RAIE T0IF INTF RCIF C2IF C1IF OSFIF TXIF RCIE C2IE C1IE OSFIE TXIE Preliminary PIC16F688 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. CY Value on Value on Bit 0 all other POR, BOD ...
Page 114
... Store the Status register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F688 normally does not require saving the PCLATH. computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR ...
Page 115
... Watchdog Timer (WDT) For PIC16F688, the WDT has been modified from previous 16F devices. The new WDT is code and functionally compatible with previous 16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time ...
Page 116
... PIC16F688 REGISTER 11-3: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h) U-0 — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) ...
Page 117
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. Preliminary PIC16F688 DS41203B-page 115 ...
Page 118
... PIC16F688 FIGURE 11-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC PC PC+1 Instruction Inst( Inst(PC) = Sleep Fetched Instruction Sleep Inst( Executed Note 1: XT Oscillator mode assumed 1024 T (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. ...
Page 119
... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. 11.11 In-Circuit Serial Programming The PIC16F688 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: • ...
Page 120
... A special debugging adapter allows the ICD device to be used in place of a PIC16F688 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC16F688 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...
Page 121
... INSTRUCTION SET SUMMARY The PIC16F688 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
Page 122
... PIC16F688 TABLE 12-2: PIC16F688 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS f, d Add W and f ADDWF f, d AND W with f ANDWF f Clear f CLRF - Clear W CLRW f, d Complement f COMF f, d Decrement f DECF f, d Decrement f, Skip if 0 DECFSZ f, d Increment f INCF f, d Increment f, Skip if 0 ...
Page 123
... Operation: Status Affected: Description: BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSS k Syntax: Operands: Operation: Status Affected: Description: f,d Preliminary PIC16F688 Bit Clear f [ label ] BCF f 127 (f<b>) None Bit ‘b’ in register ‘f’ is cleared. Bit Set f [ label ] BSF f 127 ...
Page 124
... PIC16F688 BTFSC Bit Test, Skip if Clear Syntax: [ label ] BTFSC f,b Operands 127 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction ...
Page 125
... destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example MOVF After Instruction Preliminary PIC16F688 INCFSZ f,d 127 (destination), MOVF f,d 127 1000 dfff ffff 0 FSR value in FSR ...
Page 126
... PIC16F688 MOVWF Move Syntax: [ label ] MOVWF Operands 127 Operation: (W) (f) Status Affected: None Encoding: 00 0000 Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example MOVWF OPTION Before Instruction OPTION = W = After Instruction OPTION = W = IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k ...
Page 127
... Operation: Status Affected: Encoding: 0000 1001 Description: Words: Cycles: Example TABLE RETURN Syntax: Operands: Operation: Status Affected: Description: Preliminary PIC16F688 Return with Literal label ] RETLW 255 k (W); TOS PC None 11 01xx kkkk kkkk The W register is loaded with the eight bit literal ‘k’. The program counter is loaded from the top of the stack (the return address) ...
Page 128
... PIC16F688 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Encoding: 00 1101 Description: The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘ ...
Page 129
... Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2004 Microchip Technology Inc. f,d Preliminary PIC16F688 DS41203B-page 127 ...
Page 130
... PIC16F688 NOTES: DS41203B-page 128 Preliminary 2004 Microchip Technology Inc. ...
Page 131
... The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Preliminary PIC16F688 ® ® standard HEX DS41203B-page 129 ...
Page 132
... PIC16F688 13.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 133
... MPLAB PM3 connects to the host PC via an RS- 232 or USB cable. MPLAB PM3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an SD/MMC card for file storage and secure data appli- cations. Preliminary PIC16F688 development tool, TM (ICSP TM ) ...
Page 134
... PIC16F688 13.14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...
Page 135
... PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. ® IDE software, Preliminary PIC16F688 TM development DS41203B-page 133 ...
Page 136
... PIC16F688 NOTES: DS41203B-page 134 Preliminary 2004 Microchip Technology Inc. ...
Page 137
... V 2004 Microchip Technology Inc. ........................................................................... -0. ∑ DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. should be used when applying a “low” level to the MCLR pin, rather than . SS Preliminary PIC16F688 + 0.3V ∑ {( ∑( DS41203B-page 135 ). ...
Page 138
... PIC16F688 FIGURE 14-1: PIC16F688 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41203B-page 136 Frequency (MHz) Preliminary 20 2004 Microchip Technology Inc. ...
Page 139
... DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset ...
Page 140
... PIC16F688 14.2 DC Characteristics: PIC16F688-I (Industrial) DC Characteristics Param Device Characteristics No. (1, 2) D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 D018 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 141
... DC Characteristics: PIC16F688-I (Industrial) DC Characteristics Param Device Characteristics No. D020 Power-down Base (4) Current ( D021 D022 D023 D024 D025 D026 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 142
... PIC16F688 14.4 PIC16F688 DC Characteristics: DC Characteristics Param Device Characteristics No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E D018E Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 143
... A 3.0 — 0.0022 TBD A 5 and the additional current consumed when this DD PD current can be determined by subtracting the base I Preliminary PIC16F688 +125 C for extended Conditions Note WDT, BOD, Comparators, V REF and T1OSC disabled WDT Current BOD Current (3) Comparator Current CV Current REF ...
Page 144
... PIC16F688 14.6 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O port: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) (1) D033A OSC1 (HS mode) V Input High Voltage ...
Page 145
... DC Characteristics: PIC16F688 -I (Industrial), PIC16F688 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. D100 I Ultra Low-Power Wake-up ULP Current Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write ...
Page 146
... PIC16F688 14.8 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall H High ...
Page 147
... AC Characteristics: PIC16F688 (Industrial, Extended) FIGURE 14-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C T Param Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period ...
Page 148
... PIC16F688 TABLE 14-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature-40°C T +125°C A Param Sym Characteristic No. F10 F Internal Calibrated OSC INTOSC Frequency F14 T Oscillator Wake-up from IOSC Sleep Start-up Time* ST Legend: TBD = To Be Determined * These parameters are characterized but not tested. ...
Page 149
... T + 200 ns — OSC 0 — — 50 — — 100 — 0 — — 10 — — T — CY OSC Preliminary PIC16F688 New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150* ns 300 ns — ...
Page 150
... PIC16F688 FIGURE 14-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O pins FIGURE 14-6: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in the Configuration Word is programmed to ‘ ...
Page 151
... TBD TBD TBD ms — — 2.0 s 2.025 — 2.175 V 100* — — s Preliminary PIC16F688 Conditions V = 5V, -40°C to +85°C DD Extended temperature V = 5V, -40°C to +85°C DD Extended temperature T = OSC1 period OSC V = 5V, -40°C to +85°C DD Extended Temperature V B (D005) DD VDD ...
Page 152
... PIC16F688 FIGURE 14-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 14-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width 42* Tt0P T0CKI Period 45* Tt1H T1CKI High ...
Page 153
... Microchip Technology Inc. 121 121 Characteristic Min PIC16F688 — PIC16LF688 — PIC16F688 — PIC16LF688 — PIC16F688 — PIC16LF688 — 125 126 Min (DT hold time) 10 (DT hold time) 15 Preliminary PIC16F688 122 Max Units Conditions 40 ns 100 Max Units Conditions — ns — ns DS41203B-page 151 ...
Page 154
... PIC16F688 TABLE 14-8: COMPARATOR SPECIFICATIONS Comparator Specifications Sym Characteristics V Input Offset Voltage OS V Input Common Mode Voltage CM C Common Mode Rejection Ratio MRR (1) T Response Time Comparator Mode Change Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (V ...
Page 155
... TABLE 14-10: PIC16F688 A/D CONVERTER CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating Temperature-40°C T +125°C A Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute ABS (1) Error* A03 E Integral Error IL A04 E Differential Error DL A05 E Full-scale Range FS A06 E Offset Error OFF A07 ...
Page 156
... A/D CLK A/D Data ADRES ADIF GO 132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 14-11: PIC16F688 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature-40°C T +125°C A Param Sym Characteristic No ...
Page 157
... A/D Data ADRES ADIF GO 132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 14-12: PIC16F688 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Standard Operating Conditions (unless otherwise stated) Operating Temperature-40°C T +125°C A Param Sym Characteristic No ...
Page 158
... PIC16F688 NOTES: DS41203B-page 156 Preliminary 2004 Microchip Technology Inc. ...
Page 159
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. 2004 Microchip Technology Inc. Preliminary PIC16F688 DS41203B-page 157 ...
Page 160
... PIC16F688 NOTES: DS41203B-page 158 Preliminary 2004 Microchip Technology Inc. ...
Page 161
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. Example 16F688-I 0215017 Example 16F688-E 0215017 Example 16F688 0215 017 Preliminary PIC16F688 DS41203B-page 159 ...
Page 162
... PIC16F688 16.2 Package Details The following sections give the technical details of the packages. 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...
Page 163
... L .016 .033 .050 .008 .009 .010 B .014 .017 .020 Preliminary PIC16F688 A2 MILLIMETERS MIN NOM MAX 14 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 5.99 6.20 3.81 3.90 3.99 8.56 8.69 8.81 0.25 0.38 ...
Page 164
... PIC16F688 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...
Page 165
... Microchip Technology Inc. APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC16F6XX family of devices. B.1 PIC16F676 to PIC16F688 TABLE B-1: FEATURE COMPARISON Feature Max Operating Speed Max Program Memory (Words) SRAM (Bytes) A/D Resolution ...
Page 166
... PIC16F688 NOTES: DS41203B-page 164 Preliminary 2004 Microchip Technology Inc. ...
Page 167
... Comparator Voltage Reference (CV REF Fail-Safe Clock Monitor (FSCM) ................................. 28 In-Circuit Serial Programming Connections.............. 117 Interrupt Logic ........................................................... 110 MCLR Circuit............................................................. 103 On-Chip Reset Circuit ............................................... 102 PIC16F688.................................................................... 5 RA1 Pins ..................................................................... 36 RA2 Pin....................................................................... 37 RA3 Pin....................................................................... 37 RA4 Pin....................................................................... 38 RA5 Pin....................................................................... 38 RC0 and RC1 Pins...................................................... 40 RC2 and RC3 Pins...................................................... 41 RC4 Pin ...
Page 168
... PIC16F688 D Data EEPROM Memory ...................................................... 71 Associated Registers .................................................. 75 Reading....................................................................... 73 Writing ......................................................................... 73 Data Memory......................................................................... 7 DC Characteristics Extended and Industrial ............................................ 142 Industrial and Extended ............................................ 137 Demonstration Boards PICDEM 1 ................................................................. 132 PICDEM 17 ............................................................... 133 PICDEM 18R ............................................................ 133 PICDEM 2 Plus ......................................................... 132 PICDEM 3 ................................................................. 132 PICDEM 4 ................................................................. 132 PICDEM LIN ............................................................. 133 PICDEM USB............................................................ 133 PICDEM ...
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... Computed GOTO........................................................ 19 Stack ........................................................................... 19 PCON Register ................................................................. 105 PICkit 1 Flash Starter Kit................................................... 133 PICSTART Plus Development Programmer ..................... 132 PIE1 Register ...................................................................... 16 Pin Diagram .......................................................................... 2 Pinout Description PIC16F688.................................................................... 6 PIR1 Register...................................................................... 17 PORTA................................................................................ 31 Additional Pin Functions ............................................. 31 Interrupt-on-Change ........................................... 33 Ultra Low-Power Wake-up ............................ 31, 34 Weak Pull-up ...................................................... 31 Associated Registers .................................................. 39 Pin Descriptions and Diagrams................................... 36 RA0 ...
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... PIC16F688 Timer0 Module .................................................................... 45 Timer1 Associated Registers .................................................. 52 Asynchronous Counter Mode ..................................... 52 Reading and Writing ........................................... 52 External Clock Requirements ................................... 150 Interrupt....................................................................... 50 Modes of Operations................................................... 50 Operation During Sleep .............................................. 52 Oscillator ..................................................................... 52 Prescaler ..................................................................... 50 Timer1 Gate Inverting Gate ..................................................... 50 Selecting Source........................................... 50, 58 Synchronizing C2OUT w/ Timer1 ....................... 58 TMR1H Register ......................................................... 49 TMR1L Register .......................................................... 49 Timer1 Module with Gate Control ....................................... 49 Timing Diagrams A/D Conversion ...
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... Microchip's development systems software products. Plus, this line provides information on how customers ® ® can receive the most current upgrade kits. The Hot Line or Microsoft Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Preliminary PIC16F688 042003 DS41203B-page 169 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F688 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. 2004 Microchip Technology Inc. XXX Examples: Pattern a) PIC16F688-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC16F688-I/SO = Industrial Temp., SOIC package, 20 MHz c) Preliminary PIC16F688 ...
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... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 02/17/04 2004 Microchip Technology Inc. ...