ATTINY13A-MU Atmel, ATTINY13A-MU Datasheet - Page 48

• Manufacturer Part Number: ATTINY13A-MU
• Description: IC MCU AVR 1K FLASH 20MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.3
9.3.4
48
ATtiny13A
GIFR – General Interrupt Flag Register
PCMSK – Pin Change Mask Register
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT[5:0] pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
• Bits 5:0 – PCINT[5:0]: Pin Change Enable Mask 5:0
Each PCINT[5:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[5:0] is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[5:0] is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
0x3A
Read/Write
Initial Value
Bit
0x15
Read/Write
Initial Value
R
R
7
–
0
7
–
0
INTF0
R/W
R
6
–
0
6
0
PCINT5
PCIF
R/W
R/W
5
0
5
0
PCINT4
R/W
R
4
0
4
–
0
PCINT3
R/W
R
3
0
3
–
0
PCINT2
R/W
R
2
0
2
–
0
PCINT1
R/W
R
1
0
1
–
0
PCINT0
R/W
0
0
R
0
–
0
8126E–AVR–07/10
PCMSK
GIFR