PIC16HV540-04/P Microchip Technology, PIC16HV540-04/P Datasheet - Page 19

• Manufacturer Part Number: PIC16HV540-04/P
• Description: IC MCU OTP 512X12 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16HV540-04/P

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: OTP
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 15 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16HV
• No. Of I/o's: 12
• Ram Memory Size: 25Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Digital Ic Case Style: DIP
• Processor Series: PIC16H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 25 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 8
• Operating Supply Voltage: 3.5 V to 15 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164001 - MODULE SKT PROMATEII 18/28DIP
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

5.0
As with any other register, the I/O registers can be writ-
ten and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB) are all set.
5.1
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's. The inputs will tolerate input voltages as
high as V
internal voltage regulator V
The internal regulator output, V
between 3Vdc and 5Vdc, via the (RL) bit in the
OPTION2 register.
5.2
PORTB is an 8-bit I/O register (PORTB<7:0>). All 8
PORTB I/Os are high voltage I/O. The inputs will toler-
ate input voltages as high as V
from V
be configured for the wake-up on change feature. Pins
RB0, RB1, RB2 and RB3 latch the state of the pin at the
onset of sleep mode. (No “dummy” read of the PORTB
pins is required prior to executing the SLEEP instruc-
tion.) A level change on the input resets the device,
implementing wake-up on pin change. The PCWUF bit
in the status register is cleared to indicate that a pin
change caused the reset. This feature can be enabled/
disabled in the OPTION2 register.
PORTB pin RB7 also exhibits this wake-up on pin high
feature but is specially adapted for a slow-rising input
signal. This special feature prevents excessive power
consumption when desiring long sleep periods without
using the watchdog timer and prescaler. PCWUF bit in
the status register is cleared to indicate that a pin
change caused the reset. This feature can be enabled/
disabled in the OPTION2 register.
Only pins configured as inputs can cause this wake-up
on pin change to occur.
To prevent false wake-up on pin change events on pins
RB<0:3>, the pin state must be driven to a logic 1 or
logic 0 and not left floating during the “SLEEP” state.
For pin RB7, the pin state must be driven to logic 0 and
allowed to ramp to a logic 1 for correct operation.
2000 Microchip Technology Inc.
SS
I/O PORTS
PORTA
PORTB
IO
to V
and outputs will swing from V
DD
. In addition, 5 of the PORTB pins can
IO
powers PORTA I/O pads.
DD
and outputs will swing
IO
, is switchable
SS
to V
IO
. The
Preliminary
5.3
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the corre-
sponding output driver in a hi-impedance mode. A '0'
puts the contents of the output data latch on the
selected pins, enabling the output buffer.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
5.4
The equivalent circuit for the PORTA and PORTB I/O
pins are shown in Figure 5-1 through Figure 5-4. All
ports may be used for both input and output operation.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF PORTB, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit (in TRISA, TRISB) must be cleared (= 0). For
use as an input, the corresponding TRIS bit must be
set. Any I/O pin can be programmed individually as
input or output.
Note:
TRIS Registers
I/O Interfacing
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
PIC16HV540
DS40197B-page 19