PIC16F684-I/ST Microchip Technology, PIC16F684-I/ST Datasheet
PIC16F684-I/ST
Specifications of PIC16F684-I/ST
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PIC16F684-I/ST Summary of contents
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... Microchip Technology Inc. PIC16F684 Data Sheet 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology Preliminary DS41202C ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash/Data EEPROM retention: > 40 years Program Memory Device Flash (words) PIC16F684 2048 2004 Microchip Technology Inc. PIC16F684 Low-Power Features: • Standby Current 2.0V, typical • Operating Current kHz, 2.0V, typical - 100 MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical Peripheral Features: • ...
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... PIC16F684 Pin Diagram 14-pin PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/P1C DS41202C-page RA0/AN0/C1IN+/ICSPDAT/ULPWU 13 RA1/AN1/C1IN-/ RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN RC1/AN5/C2IN RC2/AN6/P1D 7 8 Preliminary /ICSPCLK REF 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. Preliminary PIC16F684 DS41202C-page 3 ...
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... PIC16F684 NOTES: DS41202C-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... The PIC16F684 is covered by this data sheet available in 14-pin PDIP, SOIC and TSSOP packages. Figure 1-1 shows a block diagram of the PIC16F684 device. Table 1-1 shows the pinout description. ...
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... PIC16F684 TABLE 1-1: PIC16F684 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C1IN-/V /ICSPCLK RA1 REF AN1 C1IN- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI ...
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... Program Memory Organization The PIC16F684 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-07FFh) for the PIC16F684 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
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... PIC16F684 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 the PIC16F684. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1) ...
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... TABLE 2-1: PIC16F684 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s register 02h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...
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... PIC16F684 TABLE 2-2: PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...
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... Status bits. For other instructions not affecting any Status bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 (Status<7:6>) are not used by the PIC16F684 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products ...
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... PIC16F684 2.2.2.2 Option Register The Option register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External RA2/INT interrupt • TMR0 • Weak pull-ups on PORTA REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 ...
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... R/W-0 R/W-0 R/W-0 R/W-0 T0IE INTE RAIE T0IF (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 R/W-0 R/W-0 INTF RAIF bit Bit is unknown DS41202C-page 13 ...
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... PIC16F684 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt ...
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... R/W-0 R/W-0 R/W-0 R/W-0 CCP1IF C2IF C1IF OSFIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown DS41202C-page 15 ...
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... PIC16F684 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the ultra low-power wake-up and software enable of the BOD ...
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... Application Note AN556, “Implementing a Table Read” (DS00556). 2.3.2 STACK The PIC16F684 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... PIC16F684 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F684 Direct Addressing (1) From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. ...
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... Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz 2004 Microchip Technology Inc. The PIC16F684 can be configured in one of eight clock modes – External clock with I/O on RA4 – Low gain Crystal or Ceramic Resonator Oscillator mode – Medium gain Crystal or Ceramic Resona- tor Oscillator mode ...
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... External Clock Modes 3.3.1 OSCILLATOR START-UP TIMER (OST) If the PIC16F684 is configured for LP modes, the Oscillator Start-up Timer (OST) counts 1024 oscil- lations from the OSC1 pin, following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended ...
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... additional parallel feedback resistor (R may be required for proper ceramic resonator operation (typical value Internal Logic Sleep to vary Preliminary PIC16F684 CERAMIC RESONATOR OPERATION ( MODE) PIC16F684 OSC1 To Internal Logic Sleep P ( OSC2 S ( may be required for S varies with the Oscillator ...
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... The user also needs to take into account variation due to tolerance of external RC components used. DS41202C-page 22 3.4 Internal Clock Modes The PIC16F684 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ± ...
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... Monitor (FSCM) and peripherals, are not affected by the change in frequency. U-0 U-0 R/W-0 R/W-0 — — TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown DS41202C-page 23 ...
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... PIC16F684 3.4.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The ...
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... OSTS bit (OSCCON<3>) to remain clear. 2004 Microchip Technology Inc. When the PIC16F684 is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 (OST)”). The OST timer will suspend program execu- tion until 1024 oscillations are counted ...
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... PIC16F684 3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC16F684 is running from the external clock source as defined by the FOSC bits in the Configuration Word register (CONFIG) or the internal oscillator. FIGURE 3-7: TWO-SPEED START- INTOSC T T OST ...
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... The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC16F684 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. ...
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... PIC16F684 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output CM Output (Q) OSCFIF CM Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 3.7.2 RESET OR WAKE-UP FROM SLEEP ...
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... TMR2IE TMR1IE 0000 0000 0000 0000 IRCF1 IRCF0 OSTS HTS LTS — TUN4 TUN3 TUN2 TUN1 MCLRE PWRTE WDTE FOSC2 FOSC1 Preliminary PIC16F684 R-0 R-0 R/W-0 (1) HTS LTS SCS bit Bit is unknown Value on Value on: Bit 0 all other POR, BOD Resets SCS ...
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... PIC16F684 NOTES: DS41202C-page 30 Preliminary 2004 Microchip Technology Inc. ...
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... MOVWF TRISA BCF STATUS,RP0 4.2 Additional Pin Functions Every PORTA pin on the PIC16F684 has an interrupt- on-change option and a weak pull-up option. RA0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 WEAK PULL-UPS Each of the PORTA pins, except RA3, has an individu- ally configurable internal weak pull-up ...
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... PIC16F684 REGISTER 4-2: TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h) U-0 — bit 7 bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISA<5:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output Note 1: TRISA<3> always reads ‘1’. ...
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... U-0 R/W-0 R/W-0 R/W-0 — IOCA5 IOCA4 IOCA3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 R/W-0 R/W-0 R/W-0 IOCA2 IOCA1 IOCA0 bit Bit is unknown DS41202C-page 33 ...
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... PIC16F684 4.2.3 ULTRA LOW-POWER WAKE-UP The Ultra Low-power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt- on-change on RA0 without excess current consump- tion. The mode is selected by setting the ULPWUE bit (PCON<5>). This enables a small current sink which can be used to discharge a capacitor on RA0. ...
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... IOCA RD IOCA Interrupt-on- Change Note 1: Comparator mode and ANSEL determines Analog Input mode. 2004 Microchip Technology Inc. (1) Analog Input Mode RAPU - + 0 1 (1) Analog Input Mode ULPWUE PORTA To Comparator To A/D Converter Preliminary PIC16F684 V DD Weak V DD I/O PIN ULP V SS DS41202C-page 35 ...
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... PIC16F684 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet. ...
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... Master Clear Reset with weak pull-up FIGURE 4-4: Data Bus Weak TRISA RD PORTA IOCA DD RD IOCA I/O PIN Interrupt-on- Change Preliminary PIC16F684 PP BLOCK DIAGRAM OF RA3 V DD MCLRE Weak MCLRE Reset Input pin V SS MCLRE PORTA DS41202C-page 37 ...
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... PIC16F684 4.2.4.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • a TMR1 gate input • a crystal/resonator connection • a clock output FIGURE 4-5: ...
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... ANS4 ANS3 ANS2 ANS1 WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 Preliminary PIC16F684 Value on all Value on: Bit 0 other POR, BOD Resets RA0 --xx xx00 --uu uu00 RAIF 0000 0000 0000 0000 CM0 0000 0000 0000 0000 PS0 ...
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... PIC16F684 4.3 PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter or compara- tor. For specific information about individual functions such as the Enhanced CCP or the A/D, refer to the appropriate section in this data sheet ...
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... Full-bridge mode and vise-versa. FIGURE 4-9: C2OUT EN CCPOUT EN C2OUT EN C2OUT CCPOUT EN CCPOUT V DD Data Bus PORTC I/O PIN TRISC RD TRISC RD PORTC Note 1: Port/Peripheral Select signals selects between port data and peripheral output. Preliminary PIC16F684 BLOCK DIAGRAM OF RC4 I/O PIN V SS DS41202C-page 41 ...
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... PIC16F684 4.3.6 RC5/CCP1/P1A The RC5 is configurable to function as one of the following: • a general purpose I/O • a digital input/output for the Enhanced CCP FIGURE 4-10: BLOCK DIAGRAM OF RC5 PIN Data bus CCP1OUT D Q Enable CCP1OUT PORTC TRISC RD TRISC RD PORTC To Enhanced CCP DS41202C-page I/O PIN ...
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... Bit 3 Bit 2 RC5 RC4 RC3 RC2 C2INV C1INV CIS CM2 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 ANS5 ANS4 ANS3 ANS2 Preliminary PIC16F684 R/W-x R/W-0 R/W-0 RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown ...
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... PIC16F684 NOTES: DS41202C-page 44 Preliminary 2004 Microchip Technology Inc. ...
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... Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. 8-bit Prescaler PSA 8 PS<2:0> 16-bit 16 PSA WDTPS<3:0> Preliminary PIC16F684 edge (T0SE) control ® Mid-Range MCU Family Data Bus 8 1 SYNC 2 TMR0 Cycles ...
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... Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F684. See Section 12.6 “Watchdog Timer (WDT)” for more information. Legend Readable bit -n = Value at POR DS41202C-page 46 (and OSC OSC ...
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... Bit 1 T0IE INTE RAIE T0IF INTF T0CS T0SE PSA PS2 PS1 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Preliminary PIC16F684 CHANGING PRESCALER (TIMER0 WDT) ;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ...
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... PIC16F684 NOTES: DS41202C-page 48 Preliminary 2004 Microchip Technology Inc. ...
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... TIMER1 MODULE WITH GATE CONTROL The PIC16F684 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • ...
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... PIC16F684 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit Timer with prescaler • 16-bit Synchronous counter • 16-bit Asynchronous counter In Timer mode, Timer1 is incremented on every instruc- tion cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In ...
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... R = Readable bit -n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) (2) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS41202C-page 51 ...
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... PIC16F684 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor ...
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... TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W-0 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 /4) has a prescale option OSC ) h R/W-0 R/W-0 R/W-0 bit Bit is unknown DS41202C-page 53 ...
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... PIC16F684 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: ...
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... Figure 8-3. R-0 R/W-0 R/W-0 R/W-0 C2INV C1INV CIS - Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 R/W-0 R/W-0 R/W-0 CM2 CM1 CM0 bit Bit is unknown DS41202C-page 55 ...
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... PIC16F684 8.1 Comparator Operation A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... C1OUT D RA2/C1OUT A RC1/AN5 C2OUT A RC0/AN4 RC4/C2OUT Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 A RA1/AN1 Off (Read as ‘0’) A RA0/AN0 A RC1/AN5 C2OUT A RC0/AN4 CIS (CMCON0<3>) is the Comparator Input Switch Preliminary PIC16F684 Off C1 (Read as ‘0’ Off C2 (Read as ‘0’ CIS = CIS = 1 C1OUT ...
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... PIC16F684 FIGURE 8-4: INVERTIBLE COMPARATOR C1 OUTPUT BLOCK DIAGRAM To C1OUT pin To Data Bus RD CMCON Set C1IF bit FIGURE 8-5: INVERTIBLE COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2SYNC To TMR1 To C2OUT pin To Data Bus RD CMCON Set C2IF bit Note 1: Comparator 2 output is latched on falling edge of T1 clock source. ...
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... CxIF to be cleared. Note change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF (PIR1<4:3>) interrupt flag may not get set. Preliminary PIC16F684 U-0 R/W-1 R/W-0 — T1GSS C2SYNC bit 0 ...
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... PIC16F684 8.6 Comparator Reference The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register (Register 8-3) controls the voltage reference module shown in Figure 8-6. 8.6.1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels high range and low range ...
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... VRCON registers to their Reset states. This forces the comparator module the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible. Preliminary PIC16F684 DS41202C-page 61 ...
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... PIC16F684 REGISTER 8-3: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 VREN bit 7 bit 7 VREN: CV REF circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CV Range Selection bit REF 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ ...
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... The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either voltage applied by the V DD shows the block diagram of the A/D on the PIC16F684 VCFG = 0 V REF VCFG = 1 ...
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... PIC16F684 9.1.4 CONVERSION CLOCK The A/D conversion cycle requires the conversion clock is software selectable via the ADCS bits (ADCON1<6:4>). There are seven possible clock options: • OSC • OSC • OSC TABLE 9-1: T VS. DEVICE OPERATING FREQUENCIES AD A/D Clock Source ( Operation ...
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... A/D Result R/W-1 R/W-1 R/W-1 ANS5 ANS4 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown ...
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... PIC16F684 REGISTER 9-2: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 ADFM VCFG bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit pin REF bit 5 Unimplemented: Read as ‘0’ bit 4-2 CHS<2:0>: Analog Channel Select bits ...
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... MOVF ADRESH,W MOVWF RESULTHI BSF STATUS,RP0 MOVF ADRESL,W MOVWF RESULTLO is AD Preliminary PIC16F684 A/D CONVERSION ;Bank 1 ;A/D RC clock ;Set RA0 to input ;Set RA0 to analog ;Bank 0 ;Right, Vdd Vref, AN0 ;Wait min sample time ;Start conversion ;Is conversion done? ;No, test again ;Read upper 2 bits ...
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... PIC16F684 9.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to HOLD fully charge to the input channel voltage level. The ana- log input model is shown in Figure 9-4. The source impedance (R ) and the internal sampling switch (R ...
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... If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter. See Section 11.0 “Enhanced Capture/Compare/PWM (ECCP) Module” for more information. be (moving the Preliminary PIC16F684 Analog Input Voltage DS41202C-page 69 ...
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... PIC16F684 TABLE 9-2: SUMMARY OF A/D REGISTERS Addr Name Bit 7 Bit 6 Bit 5 05h PORTA — — RA5 07h PORTC — — RC5 0Bh/ INTCON GIE PEIE T0IE 8Bh 0Ch PIR1 EEIF ADIF CCP1IF 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of the right shifted result ...
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... EEDAT • EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F684 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 10-1: EEDAT – EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
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... PIC16F684 10.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non- implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software ...
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... If proper refreshes occurred, then the lone memory location would have to be refreshed six times for the data to remain correct. Preliminary PIC16F684 ;Bank 1 ;EEDAT not changed ;from previous write ;YES, Read the ...
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... PIC16F684 10.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) EEPROM write. ...
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... R/W-0 R/W-0 R/W-0 P1M0 DC1B1 DC1B0 CCP1M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 ECCP MODE – TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 ...
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... PIC16F684 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC5/CCP1/P1A. An event is defined as one of the following and is configured by CCP1CON<3:0>: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge When a capture is made, the interrupt request flag bit, CCP1IF (PIR1< ...
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... DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 TRISC4 TRISC3 TRISC2 C2IE C1IE OSFIE Preliminary PIC16F684 Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF RAIF 0000 0000 0000 0000 TMR2IF TMR1IF 0000 0000 0000 0000 ...
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... PIC16F684 11.3 Enhanced PWM Mode The Enhanced CCP module produces 10-bit resolution PWM output and may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC. The pin assignments are summarized in Table 11-3. ...
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... If the PWM duty cycle value is longer than the PWM period, the assigned PWM pin(s) will remain unchanged. (1) (1) 4.88 kHz 19.53 kHz 78.12 kHz 4 1 0xFF 0xFF 10 10 Preliminary PIC16F684 = CCPR1L:CCP1CON<5:4> (TMR2 prescale value) configured by the P1M<1:0> and CCP1M<3:0> F OSC ------------------------------------------------------------ - log ...
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... PIC16F684 FIGURE 11-4: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL CCP1CON <7:6> P1A MODULATED (SINGLE OUTPUT) 00 P1A MODULATED (Half-bridge) 10 P1B MODULATED P1A ACTIVE P1B INACTIVE (Full-bridge, 01 Forward) P1C INACTIVE P1D MODULATED P1A INACTIVE P1B MODULATED (Full-bridge, 11 Reverse) P1C ACTIVE P1D INACTIVE Relationships: • ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary PIC16F684 HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver DS41202C-page 81 ...
Page 84
... PIC16F684 11.3.5 FULL-BRIDGE MODE In Full-bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RC5/CCP1/P1A is continuously active and pin RC2/AN6/P1D is modulated. FIGURE 11-8: FULL-BRIDGE PWM OUTPUT FORWARD MODE (2) P1A Duty Cycle ...
Page 85
... Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary PIC16F684 QC FET Driver FET Driver QD DS41202C-page 83 ...
Page 86
... PIC16F684 FIGURE 11-10: PWM DIRECTION CHANGE SIGNAL P1A (Active-High) P1B (Active-High) P1C (Active-High) P1D (Active-High) DC Note 1: The direction bit in the ECCP Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals ...
Page 87
... R/W-0 PDC5 PDC4 PDC3 /4 (4*T ) cycles between the scheduled time when a PWM signal should OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 driving). The ECCPASE bit has cleared. See ) h R/W-0 R/W-0 ...
Page 88
... PIC16F684 REGISTER 11-3: ECCPAS – ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER (ADDRESS: 17 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 bit 7 bit 7 ECCPASE: ECCP Auto-shutdown Event Status bit shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits ...
Page 89
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary PIC16F684 PWM Resumes ECCPASE Cleared by Firmware PWM Resumes DS41202C-page 87 ...
Page 90
... PIC16F684 11.3.9 OPERATION IN SLEEP MODE In Sleep mode, all clock sources are disabled. Timer2 will not increment, and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. ...
Page 91
... CCP1M2 PDC5 PDC4 PDC3 PDC2 ECCPAS0 PSSAC1 PSSAC0 TRISC5 TRISC4 TRISC3 TRISC2 CCP1IE C2IE C1IE OSFIE Preliminary PIC16F684 Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF RAIF 0000 0000 0000 0000 TMR2IF TMR1IF 0000 0000 0000 0000 0000 0000 ...
Page 92
... PIC16F684 NOTES: DS41202C-page 90 Preliminary 2004 Microchip Technology Inc. ...
Page 93
... SPECIAL FEATURES OF THE CPU The PIC16F684 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD) • ...
Page 94
... PIC16F684 12.1 Configuration Bits The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. REGISTER 12-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) — ...
Page 95
... See “PIC12F6XX/16F6XX Memory (DS41204) for more information not — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F684 memory space (2000h- Programming Specification” POR1 POR0 BOD2 BOD1 BOD0 bit Bit is unknown DS41202C-page 93 ...
Page 96
... PIC16F684 12.3 Reset The PIC16F684 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Detect (BOD) Some registers are not affected in any Reset condition; ...
Page 97
... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC16F684 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
Page 98
... V BOD (Section 15 Reset. 12.3.6 BOD CALIBRATION The PIC16F684 stores the BOD calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified bulk erase sequence in the “PIC12F6XX/ 16F6XX Memory (DS41204) and thus, does not require reprogramming. ...
Page 99
... Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC16F684 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers ...
Page 100
... PIC16F684 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH V ...
Page 101
... Preliminary PIC16F684 Interrupt WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu --uu uuuu ---u uuuu (2) uuuu uuuu ...
Page 102
... PIC16F684 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Power-on Register Address Reset WPUA 95h --11 -111 IOCA 96h --00 0000 VRCON 99h 0-0- 0000 EEDAT 9Ah 0000 0000 EEADR 9Bh 0000 0000 EECON1 9Ch ---- x000 EECON2 9Dh ---- ---- ADRESL 9Eh xxxx xxxx ADCON1 9Fh -000 ---- Legend unchanged unknown, — ...
Page 103
... Interrupts The PIC16F684 has 11 sources of interrupt: • External Interrupt RA2/INT • TMR0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • ...
Page 104
... PIC16F684 12.4.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. FIGURE 12-7: INTERRUPT LOGIC IOC-RA0 IOCA0 IOC-RA1 ...
Page 105
... INTE RAIE T0IF INTF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000 Preliminary PIC16F684 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. Latency CY Value on ...
Page 106
... Store the Status register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F684 normally does not require saving the PCLATH. computed GOTOs are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR ...
Page 107
... Watchdog Timer (WDT) For PIC16F684, the WDT has been modified from previous PIC16 devices. The new WDT is code and functionally compatible with previous PIC16 WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time ...
Page 108
... PIC16F684 REGISTER 12-3: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h) U-0 — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) ...
Page 109
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. Preliminary PIC16F684 DS41202C-page 107 ...
Page 110
... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. 12.10 In-Circuit Serial Programming The PIC16F684 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: • ...
Page 111
... A special debugging adapter allows the ICD device to be used in place of a PIC16F684 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC16F684 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...
Page 112
... PIC16F684 NOTES: DS41202C-page 110 Preliminary 2004 Microchip Technology Inc. ...
Page 113
... INSTRUCTION SET SUMMARY The PIC16F684 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
Page 114
... PIC16F684 TABLE 13-2: PIC16F684 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...
Page 115
... Operation: Status Affected: Description: BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSC Syntax: k Operands: Operation: Status Affected: Description: f,d Preliminary PIC16F684 Bit Clear f [ label ] BCF f 127 (f<b>) None Bit ‘b’ in register ‘f’ is cleared. Bit Set f [ label ] BSF f 127 ...
Page 116
... PIC16F684 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...
Page 117
... Status Affected: Z Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Preliminary PIC16F684 INCFSZ f,d 127 (destination), IORLW k 255 (W) IORWF f,d 127 ...
Page 118
... PIC16F684 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...
Page 119
... Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example RLF Before Instruction After Instruction Preliminary PIC16F684 RETURN PC RLF f,d 127 C Register f REG1,0 REG1 = 1110 0110 C ...
Page 120
... PIC16F684 RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. ...
Page 121
... Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2004 Microchip Technology Inc. f,d Preliminary PIC16F684 DS41202C-page 119 ...
Page 122
... PIC16F684 NOTES: DS41202C-page 120 Preliminary 2004 Microchip Technology Inc. ...
Page 123
... The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Preliminary PIC16F684 ® ® standard HEX DS41202C-page 121 ...
Page 124
... PIC16F684 14.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 125
... MPLAB PM3 connects to the host PC via an RS- 232 or USB cable. MPLAB PM3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an SD/MMC card for file storage and secure data appli- cations. Preliminary PIC16F684 development tool, TM (ICSP TM ) ...
Page 126
... PIC16F684 14.14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...
Page 127
... PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. ® IDE software, Preliminary PIC16F684 TM development DS41202C-page 125 ...
Page 128
... PIC16F684 NOTES: DS41202C-page 126 Preliminary 2004 Microchip Technology Inc. ...
Page 129
... V 2004 Microchip Technology Inc. ........................................................................... -0. – ∑ DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. should be used when applying a “low” level to the MCLR pin, rather than . SS Preliminary PIC16F684 + 0.3V ∑ {( ∑(V – DS41202C-page 127 ...
Page 130
... PIC16F684 FIGURE 15-1: PIC16F684 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41202C-page 128 Frequency (MHz) Preliminary 20 2004 Microchip Technology Inc. ...
Page 131
... DC Characteristics: PIC16F684 -I (Industrial) PIC16F684 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset ...
Page 132
... PIC16F684 15.2 DC Characteristics: PIC16F684-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 D018 Legend: TBD = To Be Determined. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 133
... DC Characteristics: PIC16F684-I (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (4) Current D021 D022 D023 D024 D025 D026 Legend: TBD = To Be Determined. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 134
... PIC16F684 15.3 PIC16F684 DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics Min No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E D018E Legend: TBD = To Be Determined. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 135
... OSC1 = external square wave, ; MCLR = V ; WDT disabled and the additional current consumed when this DD PD current can be determined by subtracting the base I Preliminary PIC16F684 Conditions Note WDT, BOD, Comparators, V and REF T1OSC disabled WDT Current BOD Current (3) Comparator Current ...
Page 136
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. DS41202C-page 134 PIC16F684 -I (Industrial) PIC16F684 -E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...
Page 137
... Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 2004 Microchip Technology Inc. PIC16F684 -I (Industrial) PIC16F684 -E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...
Page 138
... PIC16F684 15.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
Page 139
... AC Characteristics: PIC16F684 (Industrial, Extended) FIGURE 15-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period ...
Page 140
... PIC16F684 TABLE 15-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. F10 F Internal Calibrated OSC INTOSC Frequency F14 T Oscillator Wake-up from IOSC Sleep Start-up Time* ST Legend: TBD = To Be Determined. * These parameters are characterized but not tested. ...
Page 141
... Measurements are taken in RC mode where CLKOUT output 2004 Microchip Technology Inc. +125°C Min — — — — — 200 ns OSC 0 — — 100 0 — — Preliminary PIC16F684 Typ† Max Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ns (Note 1) 35 100 ns (Note 1) — (Note 1) — ...
Page 142
... PIC16F684 FIGURE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O pins FIGURE 15-6: BROWN-OUT DETECT TIMING AND CHARACTERISTICS BOD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in the Configuration Word register is programmed to ‘ ...
Page 143
... OSC 28* 64 132* TBD TBD TBD — — 2.0 2.025 — 2.175 100* — — Preliminary PIC16F684 Conditions 5V, -40°C to +85° Extended temperature 5V, -40°C to +85° Extended temperature — OSC1 period OSC 5V, -40°C to +85°C ...
Page 144
... PIC16F684 FIGURE 15-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width ...
Page 145
... Max — 5 — V – 1.5 DD +55* — — — 150 400* — — 10* – 1.5)/2 while the other input transitions from DD Preliminary PIC16F684 Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — prescale value ( 16) ...
Page 146
... Unit Resistor Value (R) (1) Settling Time * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. TABLE 15-9: PIC16F684 A/D CONVERTER CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No ...
Page 147
... FIGURE 15-9: PIC16F684 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (T OSC Q4 A/D CLK A/D Data ADRES ADIF GO 132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 15-10: PIC16F684 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 148
... A/D CLK A/D Data ADRES ADIF GO 132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 15-11: PIC16F684 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No ...
Page 149
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. 2004 Microchip Technology Inc. Preliminary PIC16F684 DS41202C-page 147 ...
Page 150
... PIC16F684 NOTES: DS41202C-page 148 Preliminary 2004 Microchip Technology Inc. ...
Page 151
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. Example 16F684-I 0415017 Example 16F684-E 0415017 Example 16F684 0415 017 Preliminary PIC16F684 DS41202C-page 149 ...
Page 152
... PIC16F684 17.2 Package Details The following sections give the technical details of the packages. 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...
Page 153
... L .016 .033 .050 .008 .009 .010 B .014 .017 .020 Preliminary PIC16F684 A2 MILLIMETERS MIN NOM MAX 14 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 5.99 6.20 3.81 3.90 3.99 8.56 8.69 8.81 0.25 0.38 ...
Page 154
... PIC16F684 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...
Page 155
... Microchip Technology Inc. APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC16F6XX Family of devices. B.1 PIC16F676 to PIC16F684 TABLE B-1: FEATURE COMPARISON Feature Max Operating Speed Max Program Memory (Words) SRAM (bytes) A/D Resolution ...
Page 156
... PIC16F684 NOTES: DS41202C-page 154 Preliminary 2004 Microchip Technology Inc. ...
Page 157
... Comparator Voltage Reference (CV REF Compare ..................................................................... 77 Fail-Safe Clock Monitor (FSCM) ................................. 27 In-Circuit Serial Programming Connections.............. 109 Interrupt Logic ........................................................... 102 MCLR Circuit............................................................... 95 On-Chip Reset Circuit ................................................. 94 PIC16F684.................................................................... 5 PWM (Enhanced)........................................................ 78 RA0 Pins ..................................................................... 35 RA1 Pins ..................................................................... 36 RA2 Pin....................................................................... 37 RA3 Pin....................................................................... 37 RA4 Pin....................................................................... 38 RA5 Pin....................................................................... 38 RC0 and RC1 Pins...................................................... 40 RC2 and RC3 Pins ...
Page 158
... PIC16F684 D Data EEPROM Memory Associated Registers .................................................. 74 Code Protection .................................................... 71, 74 Data Memory......................................................................... 7 DC Characteristics Extended and Industrial ............................................ 134 Industrial and Extended ............................................ 129 Demonstration Boards PICDEM 1 ................................................................. 124 PICDEM 17 ............................................................... 125 PICDEM 18R ............................................................ 125 PICDEM 2 Plus ......................................................... 124 PICDEM 3 ................................................................. 124 PICDEM 4 ................................................................. 124 PICDEM LIN ............................................................. 125 PICDEM USB............................................................ 125 PICDEM ...
Page 159
... Stack ........................................................................... 17 PCON Register ................................................................... 97 PICkit 1 Flash Starter Kit................................................... 125 PICSTART Plus Development Programmer ..................... 124 2004 Microchip Technology Inc. PIE1 Register ..................................................................... 14 Pin Diagram .......................................................................... 2 Pinout Descriptions PIC16F684 ................................................................... 6 PIR1 Register ..................................................................... 15 PORTA ............................................................................... 31 Additional Pin Functions ............................................. 31 Interrupt-on-Change ........................................... 33 Ultra Low-Power Wake-up............................ 31, 34 Weak Pull-up ...................................................... 31 Associated registers ................................................... 39 Pin Descriptions and Diagrams .................................. 36 RA0 ...
Page 160
... PIC16F684 PIE1 (Peripheral Interrupt Enable 1) ........................... 14 PIR1 (Peripheral Interrupt Register 1) ........................ 15 PORTA........................................................................ 31 PORTC ....................................................................... 43 PWM1CON (Enhanced PWM Configuration) ............. 85 Reset Values............................................................... 99 Reset Values (special registers) ............................... 100 Special Function Registers ........................................... 8 Special Register Summary ......................................... 10 Status .......................................................................... 11 T1CON (Timer1 Control)............................................. 51 T2CON (Timer2 Control)............................................. 53 TRISA (Tri-state PORTA) ........................................... 32 TRISC (Tri-state PORTC) ........................................... 43 VRCON (Voltage Reference Control) ...
Page 161
... Microchip’s development systems software products. Plus, this line provides information on how customers ® ® can receive the most current upgrade kits. The Hot Line or Microsoft Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Preliminary PIC16F684 042003 DS41202C-page 159 ...
Page 162
... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F684 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
Page 163
... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. 2004 Microchip Technology Inc. XXX Examples: Pattern a) PIC16F684-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC16F684-I/SO = Industrial Temp., SOIC package, 20 MHz Preliminary PIC16F684 ...
Page 164
... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 05/28/04 2004 Microchip Technology Inc. ...