PIC16F684-I/ST Microchip Technology, PIC16F684-I/ST Datasheet - Page 75

• Manufacturer Part Number: PIC16F684-I/ST
• Description: IC PIC MCU FLASH 2KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F684-I/ST

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 14-TSSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOP
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 10-1. The
data is available, in the very next cycle, in the EEDAT
register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 10-1:
10.3
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 10-2.
EXAMPLE 10-2:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
 2004 Microchip Technology Inc.
BSF
MOVLW
MOVWF
BSF
MOVF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Reading the EEPROM Data
Memory
Writing to the EEPROM Data
Memory
STATUS,RP0
EECON1,WREN ;Enable write
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
STATUS,RP0 ;Bank 1
CONFIG_ADDR ;
EEADR
EECON1,RD
EEDAT,W
DATA EEPROM READ
DATA EEPROM WRITE
;Bank 1
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
;Address to read
;EE Read
;Move data to W
Preliminary
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR1<7>) register must be cleared by software.
10.4
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 10-3) to the
desired value to be written.
EXAMPLE 10-3:
10.4.1
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently
endurance for any EEPROM cell is specified as Dxxx.
D120 or D120A specify a maximum number of writes to
any EEPROM location before a refresh is required of
infrequently changing memory locations.
10.4.2
A hypothetical data EEPROM is 64 bytes long and has
an endurance of 1M writes. It also has a refresh param-
eter of 10M writes. If every memory location in the cell
were written the maximum number of times, the data
EEPROM would fail after 64M write cycles. If every
memory location save one were written the maximum
number of times, the data EEPROM would fail after
63M write cycles, but the one remaining location could
fail after 10M cycles. If proper refreshes occurred, then
the lone memory location would have to be refreshed
six times for the data to remain correct.
BSF
MOVF
BSF
XORWF
BTFSS
GOTO
:
Write Verify
USING THE DATA EEPROM
EEPROM ENDURANCE
changing
STATUS,RP0
EEDAT,W
EECON1,RD
EEDAT,W
STATUS,Z
WRITE_ERR
WRITE VERIFY
information.
PIC16F684
;Bank 1
;EEDAT not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
DS41202C-page 73
The
maximum