PIC12CE519-04I/SM Microchip Technology, PIC12CE519-04I/SM Datasheet - Page 529

• Manufacturer Part Number: PIC12CE519-04I/SM
• Description: IC MCU OTP 1KX12 W/EE 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE519-04I/SM

• Core Size: 8-Bit
• Program Memory Size: 1.5KB (1K x 12)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 41Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

29.4
1997 Microchip Technology Inc.
Q Cycle Activity
Tosc
Each instruction cycle (Tcy) is comprised of four Q cycles (Q1-Q4). The Q cycle is the same as
the device oscillator cycle (T
Read, Process Data, Write etc., of each instruction cycle. The following diagram shows the rela-
tionship of the Q cycles to the instruction cycle.
The four Q cycles that make up an instruction cycle (Tcy) can be generalized as:
Each instruction will show the detailed Q cycle operation for the instruction.
Figure 29-2: Q Cycle Activity
Q1: Instruction Decode Cycle or forced No Operation
Q2: Instruction Read Cycle or No Operation
Q3: Process the Data
Q4: Instruction Write Cycle or No Operation
Q1
Q2
Tcy1
Q3
Q4
Section 29. Instruction Set
OSC
Q1
). The Q cycles provide the timing/designation for the Decode,
Q2
Tcy2
Q3
Q4
Q1
Q2
Tcy3
Q3
Q4
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