PIC16LF723-I/ML Microchip Technology, PIC16LF723-I/ML Datasheet - Page 102

• Manufacturer Part Number: PIC16LF723-I/ML
• Description: IC PIC MCU FLASH 8KX14 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• Ram Memory Size: 192Byte
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To
• Rohs Compliant: Yes
• Core: PIC
• Processor Series: PIC16LF
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 32 KHz
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 11
• Height: 0.88 mm
• Interface Type: I2C, SCI, SPI
• Length: 6 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Width: 6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F72X/PIC16LF72X
9.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the INT-
CON register are enabled, execution will switch to the
Interrupt Service Routine.
Please refer to Section 9.1.5 “Interrupts” for more
information.
9.2
9.2.1
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
9.2.2
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRES register with new conversion
DS41341E-page 102
Note:
result
Note 1: The ADIF bit is set at the completion of
2: The ADC operates during Sleep only
ADC Operation
STARTING A CONVERSION
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 9.2.6 “A/D Conversion
Procedure”.
COMPLETION OF A CONVERSION
INTERRUPTS
every conversion, regardless of whether
or not the ADC interrupt is enabled.
when the F
RC
oscillator is selected.
9.2.3
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRES register will be updated with the partially com-
plete Analog-to-Digital conversion sample. Incomplete
bits will match the last bit converted.
9.2.4
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the F
option. When the F
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
F
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
9.2.5
The Special Event Trigger of the CCP module allows
periodic ADC measurements without software inter-
vention. When this trigger occurs, the GO/DONE bit is
set by hardware and the Timer1 counter resets to zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Refer
(CCP) Module” for more information.
RC
Note:
, a SLEEP instruction causes the present conver-
to
TERMINATING A CONVERSION
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
ADC OPERATION DURING SLEEP
SPECIAL EVENT TRIGGER
Section 15.0
RC
© 2009 Microchip Technology Inc.
clock source is selected, the
“Capture/Compare/PWM
RC