PIC16LF723-I/ML Microchip Technology, PIC16LF723-I/ML Datasheet - Page 177

• Manufacturer Part Number: PIC16LF723-I/ML
• Description: IC PIC MCU FLASH 8KX14 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• Ram Memory Size: 192Byte
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To
• Rohs Compliant: Yes
• Core: PIC
• Processor Series: PIC16LF
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 32 KHz
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 11
• Height: 0.88 mm
• Interface Type: I2C, SCI, SPI
• Length: 6 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Width: 6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.2
The SSP module, in I
functions, except general call support. It provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the I
specifications:
• I
• I
• Start and Stop bit interrupts enabled to support
• Address masking
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin’s data direction bits as inputs in
the appropriate TRIS register. Upon enabling I
mode, the I
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
Data is sampled on the rising edge and shifted out on
the falling edge of the clock. This ensures that the SDA
signal is valid during the SCL high time. The SCL clock
input must have minimum high and low times for proper
operation.
Specifications”.
FIGURE 17-7:
© 2009 Microchip Technology Inc.
firmware Master mode
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
SDA
SCL
I
2
C Mode
2
C slew rate limiters in the I/O pads are
Refer
Read
Shift
Clock
MSb
to
2
I
DIAGRAM
2
C mode, implements all slave
SSPMSK Reg
SSPADD Reg
Match Detect
C™ MODE BLOCK
Stop bit Detect
SSPBUF Reg
SSPSR Reg
Section 23.0
Start and
2
C Standard mode
LSb
Write
Addr Match
Internal
Data Bus
“Electrical
2
C
PIC16F72X/PIC16LF72X
FIGURE 17-8:
The SSP module has six registers for I
They are:
• SSP Control (SSPCON) register
• SSP Status (SSPSTAT) register
• Serial Receive/Transmit Buffer (SSPBUF) register
• SSP Shift Register (SSPSR), not directly
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
17.2.1
Selection of I
SSPCON register set, forces the SCL and SDA pins to
be open drain, provided these pins are programmed as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the output
data, when required, such as for Acknowledge and
slave-transmitter sequences.
accessible
Note:
Master
HARDWARE SETUP
Pull-up
externally to the SCL and SDA pins for
proper operation of the I
SDA
SCL
2
C mode, with the SSPEN bit of the
V
resistors
TYPICAL I
CONNECTIONS
DD
V
DD
must
2
DS41341E-page 177
C™
2
C module.
SDA
SDA
SCL
SCL
(optional)
Slave 1
Slave 2
be
2
C operation.
provided