PIC18LF13K22-I/SS Microchip Technology, PIC18LF13K22-I/SS Datasheet - Page 204

• Manufacturer Part Number: PIC18LF13K22-I/SS
• Description: IC PIC MCU FLASH 256KX8 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
15.4.2
The following bits are used to configure the EUSART
for synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
15.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 15-9:
DS41365D-page 204
BAUDCON
INTCON
IPR1
PIE1
PIR1
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Name
are
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
EUSART Baud Rate Generator Register, Low Byte
EUSART Baud Rate Generator Register, High Byte
EUSART Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
identical
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
—
—
TRISC6
RCIDL
ADIP
ADIE
ADIF
Bit 6
RX9
TX9
(see
Section 15.4.1.3
TRISC5
DTRXP
SREN
TXEN
RCIP
RCIE
RCIF
Bit 5
Preliminary
TRISC4
CKTXP
INT0IE
CREN
SYNC
TXIP
TXIE
Bit 4
TXIF
ADDEN
TRISC3
SENDB
BRG16
RABIE
SSPIP
SSPIE
SSPIF
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
15.4.2.2
1.
2.
3.
4.
5.
6.
7.
Bit 3
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR0IF
CCP1IP
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
transmission
Bit 2
—
Synchronous Slave Transmission
Set-up:
TMR2IP
TMR2IE
TMR2IF
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
 2010 Microchip Technology Inc.
by
writing
TMR1IP
TMR1IE
TMR1IF
TRISC0
ABDEN
RABIF
RX9D
TX9D
Bit 0
the
on page
Values
Reset
Least
259
260
260
260
259
260
259
257
259
259
259