PIC18LF13K22-I/SS Microchip Technology, PIC18LF13K22-I/SS Datasheet - Page 382

• Manufacturer Part Number: PIC18LF13K22-I/SS
• Description: IC PIC MCU FLASH 256KX8 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
Timer3 ............................................................................... 109
Timing Diagrams
DS41365D-page 382
Interrupt..................................................................... 108
Operation .................................................................. 107
Output ....................................................................... 108
16-Bit Read/Write Mode............................................ 112
Associated Registers ................................................ 112
Operation .................................................................. 110
Oscillator ........................................................... 109, 112
Overflow Interrupt ............................................. 109, 112
Special Event Trigger (CCP)..................................... 112
TMR3H Register ....................................................... 109
TMR3L Register ........................................................ 109
A/D Conversion ......................................................... 357
Acknowledge Sequence ........................................... 170
Asynchronous Reception .......................................... 186
Asynchronous Transmission ..................................... 182
Asynchronous Transmission (Back to Back) ............ 183
Auto Wake-up Bit (WUE) During Normal Operation . 197
Auto Wake-up Bit (WUE) During Sleep .................... 197
Automatic Baud Rate Calculator ............................... 195
Baud Rate Generator with Clock Arbitration ............. 164
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ............................................ 353
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 173
Bus Collision During a Stop Condition (Case 1) ....... 176
Bus Collision During a Stop Condition (Case 2) ....... 176
Bus Collision During Start Condition (SDA only) ...... 172
Bus Collision for Transmit and Acknowledge............ 171
CLKOUT and I/O....................................................... 352
Clock Synchronization .............................................. 157
Clock Timing ............................................................. 349
Clock/Instruction Cycle ............................................... 31
Comparator Output ................................................... 221
Enhanced Capture/Compare/PWM (ECCP) ............. 356
Fail-Safe Clock Monitor (FSCM) ................................. 26
First Start Bit Timing ................................................. 165
Full-Bridge PWM Output ........................................... 122
Half-Bridge PWM Output .................................. 120, 128
I
I
I
I
I
I
I
I
I
I
I
I
Internal Oscillator Switch Timing................................. 23
PWM Auto-shutdown
PWM Direction Change ............................................ 123
PWM Direction Change at Near 100% Duty Cycle ... 124
PWM Output (Active-High)........................................ 118
PWM Output (Active-Low) ........................................ 119
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................. 363
C Bus Start/Stop Bits.............................................. 362
C Master Mode (7 or 10-Bit Transmission) ............ 168
C Master Mode (7-Bit Reception) ........................... 169
C Slave Mode (10-Bit Reception, SEN = 0) ........... 152
C Slave Mode (10-Bit Reception, SEN = 1) ........... 159
C Slave Mode (10-Bit Transmission)...................... 153
C Slave Mode (7-bit Reception, SEN = 0).............. 150
C Slave Mode (7-Bit Reception, SEN = 1) ............. 158
C Slave Mode (7-Bit Transmission)........................ 151
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ......... 170
Condition........................................................... 173
(Case 1) ............................................................ 174
(Case 2) ............................................................ 175
Auto-restart Enabled ......................................... 127
Firmware Restart .............................................. 126
(7 or 10-Bit Address Mode).............................. 160
Preliminary
Timing Diagrams and Specifications
Timing Parameter Symbology .......................................... 348
Timing Requirements
Top-of-Stack Access........................................................... 28
TRISA Register................................................................... 81
TRISB Register............................................................. 86, 90
TSTFSZ ............................................................................ 317
Two-Speed Start-up.......................................................... 261
Two-Word Instructions
TXREG ............................................................................. 181
TXSTA Register................................................................ 188
U
USART
V
Voltage Reference (VR)
Voltage Reference. See Comparator Voltage Reference
Voltage References
Repeat Start Condition ............................................. 166
Reset, WDT, OST and Power-up Timer ................... 353
Send Break Character Sequence ............................. 198
Slave Synchronization .............................................. 141
Slow Rise Time (MCLR Tied to V
SPI Master Mode (CKE = 1, SMP = 1) ..................... 360
SPI Mode (Master Mode).......................................... 140
SPI Mode (Slave Mode, CKE = 0) ............................ 142
SPI Mode (Slave Mode, CKE = 1) ............................ 142
SPI Slave Mode (CKE = 0) ....................................... 361
SPI Slave Mode (CKE = 1) ....................................... 361
Synchronous Reception (Master Mode, SREN) ....... 202
Synchronous Transmission ...................................... 200
Synchronous Transmission (Through TXEN) ........... 200
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock ........................... 355
Transition for Entry to Sleep Mode ........................... 235
Transition for Wake from Sleep (HSPLL) ................. 235
Transition Timing for Entry to Idle Mode................... 236
Transition Timing for Wake from Idle to Run Mode .. 236
USART Synchronous Receive (Master/Slave) ......... 359
USART Synchronous Transmission
A/D Conversion Requirements ................................. 357
PLL Clock ................................................................. 351
I
I2C Bus Start/Stop Bits ............................................. 363
SPI Mode .................................................................. 362
Example Cases........................................................... 32
BRGH Bit .................................................................. 191
Synchronous Master Mode
Specifications ........................................................... 358
(CV
Fixed Voltage Reference (FVR)................................ 244
VR Stabilization ........................................................ 244
2
C Bus Data............................................................. 364
REF
T
(MCLR Tied to V
Not Tied to V
Not Tied to V
Tied to V
(Master/Slave) .................................................. 359
Requirements, Synchronous Receive .............. 359
Requirements, Synchronous Transmission...... 359
Timing Diagram, Synchronous Receive ........... 359
Timing Diagram, Synchronous Transmission... 359
PWRT
)
).............................................................. 255
DD
, V
DD
DD
DD
, Case 1) .................................. 254
, Case 2) .................................. 254
 2010 Microchip Technology Inc.
DD
Rise < T
) ......................................... 255
PWRT
DD
, V
) ...................... 254
DD
Rise >