AT89LP2052-20PU Atmel, AT89LP2052-20PU Datasheet - Page 75

• Manufacturer Part Number: AT89LP2052-20PU
• Description: IC 8051 MCU FLASH 2K 20DIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP2052-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Package: 20PDIP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Cpu Family: AT89
• Device Core Size: 8b
• Frequency (max): 20MHz
• Total Internal Ram Size: 256Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.4V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.5.2
23.5.3
3547J–MICRO–10/09
Power-down Sequence
ISP Start Sequence
Execute this sequence to power-down the device after serial programming.
Figure 23-23. Serial Programming Power-down Sequence
Note:
Execute this sequence to enter ISP when the device is already operational.
Figure 23-24. In-System Programming (ISP) Start Sequence
1. Tri-state MOSI (P1.5).
2. Bring SCK (P1.7) to “L”.
3. Bring RST to “L”.
4. Bring SS (P1.4) to “L”
5. Power off Vcc.
1. Bring SS (P1.4) to “H”.
2. Tri-state MISO (P1.6).
3. Bring RST to “H”.
4. Bring SCK (P1.7) to “L”.
The waveforms on this page are not to scale.
XTAL1
MISO
MOSI
MISO
MOSI
SCK
RST
RST
SCK
V
V
SS
SS
CC
CC
HIGH Z
AT89LP2052/LP4052
HIGH Z
HIGH Z
HIGH Z
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