PIC12C671-04/SM Microchip Technology, PIC12C671-04/SM Datasheet - Page 311

• Manufacturer Part Number: PIC12C671-04/SM
• Description: IC MCU OTP 1KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C671-04/SM

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 4 Channel
• Package: 8SOIJ
• Device Core: PIC
• Family Name: PIC12
• Maximum Speed: 4 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

17.4.10.1 WCOL Status Flag
1997 Microchip Technology Inc.
If the user writes the SSPBUF when a Repeated Start sequence is in progress, then WCOL is
set and the contents of the buffer are unchanged (the write doesn’t occur).
Figure 17-22: Repeat Start Condition Waveform
Note:
Falling edge of ninth clock
SDA
SCL
Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2
is disabled until the Repeated Start condition is complete.
End of Xmit
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
Preliminary
T
SDA = 1,
SCL = 1
BRG
T
BRG
Section 17. MSSP
Sr = Repeated Start
T
BRG
At completion of start bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
and set SSPIF
Write to SSPBUF occurs here.
T
BRG
1st Bit
T
BRG
DS31017A-page 17-35
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