PIC24F16KA101-I/SS Microchip Technology, PIC24F16KA101-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC24F16KA101-I/SS
• Description: IC PIC MCU FLASH 16K 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA101-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24F16KA102 FAMILY
11. Module: Comparator (I/O Pins)
12. Module: Comparator
DS80473F-page 6
Certain I/O pins may not function correctly as
digital inputs or outputs after specific comparator
outputs have been enabled with the COE bit
(CMxCON<14> = 1). These are:
•
•
This condition may continue even after the com-
parator in question has been disabled, using the
corresponding CON bit (CMxCON<15> = 0).
Work around
In addition to clearing the CON bit, also clear the
COE bit.
Affected Silicon Revisions
When a comparator is programmed to trig-
ger
(CMxCON<7:6> = 10 or 01), setting the CPOL
bit
comparator to flag the opposite edge-detect
event (e.g., a high-to-low edge instead of the
programmed low-to-high).
Work around
Leave CPOL = 0. In addition, use the opposite
setting of CMxCON<7:6> to achieve the correct
response (e.g., use ‘10’ for ‘01’).
Affected Silicon Revisions
A5
A5
X
X
RB14 (with Comparator 1)
RA6 (with Comparator 2)
(CMxCON<13> = 1)
on
A6
A6
X
X
certain
A7
A7
X
X
B0
B0
X
X
edge-detect
may
cause
events
the
13. Module: Core (Doze Mode)
Operations that immediately follow any manipu-
lations of the DOZE<2:0> or DOZEN bits
(CLDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this
interval.
Work around
Always insert a NOP instruction before and after
either of the following:
•
•
Affected Silicon Revisions
A5
X
Enabling or disabling Doze mode by setting
or clearing the DOZEN bit
Before or after changing the DOZE<2:0> bits
A6
X
A7
X
 2010 Microchip Technology Inc.
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