PIC18F24J11-I/SO Microchip Technology, PIC18F24J11-I/SO Datasheet - Page 276

• Manufacturer Part Number: PIC18F24J11-I/SO
• Description: IC PIC MCU FLASH 16K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24J11-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILAC164332 - MODULE SKT FOR 28SOIC 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
18.4
The SPI DMA module contains control logic to allow the
MSSP2 module to perform SPI direct memory access
transfers. This enables the module to quickly transmit
or receive large amounts of data with relatively little
CPU intervention. When the SPI DMA module is used,
MSSP2 can directly read and write to general purpose
SRAM. When the SPI DMA module is not enabled,
MSSP2 functions normally, but without DMA capability.
The SPI DMA module is composed of control logic, a
Destination Receive Address Pointer, a Transmit
Source Address Pointer, an interrupt manager and a
Byte Count register for setting the size of each DMA
transfer. The DMA module may be used with all SPI
Master and Slave modes, and supports both
half-duplex and full-duplex transfers.
18.4.1
When enabled, the SPI DMA module uses the MSSP2
module. All SPI related input and output signals related
to MSSP2 are routed through the Peripheral Pin Select
module. The appropriate initialization procedure as
described in Section 18.4.6 “Using the SPI DMA
Module” will need to be followed prior to using the SPI
DMA module. The output pins assigned to the SDO2
and SCK2 functions can optionally be configured as
open-drain outputs, such as for level shifting operations
mentioned in the same section.
18.4.2
Although the SPI DMA module is primarily intended to
be used for SPI communication purposes, the module
can also be used to perform RAM to RAM copy opera-
tions. To do this, configure the module for Full-Duplex
Master mode operation, but assign the SDO2 output
and SDI2 input functions onto the same RPn pin in the
PPS module. This will allow the module to operate in
Loopback mode, providing RAM copy capability.
18.4.3
The SPI DMA module remains fully functional when the
microcontroller is in Idle mode.
During normal sleep, the SPI DMA module is not func-
tional and should not be used. To avoid corrupting a
transfer, user firmware should be careful to make
certain that pending DMA operations are complete by
polling the DMAEN bit in the DMACON1 register prior
to putting the microcontroller into Sleep.
DS39932C-page 276
SPI DMA Module
I/O PIN CONSIDERATIONS
RAM TO RAM COPY OPERATIONS
IDLE AND SLEEP
CONSIDERATIONS
In SPI Slave modes, the MSSP2 module is capable of
transmitting and/or receiving one byte of data while in
Sleep mode. This allows the SSP2IF flag in the PIR3
register to be used as a wake-up source. When the
DMAEN bit is cleared, the SPI DMA module is
effectively disabled, and the MSSP2 module functions
normally, but without DMA capabilities. If the DMAEN
bit is clear prior to entering Sleep, it is still possible to
use the SSP2IF as a wake-up source without any data
loss.
Neither MSSP2 nor the SPI DMA module will provide
any functionality in Deep Sleep. Upon exiting from
Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA
related registers will need to be fully reinitialized before
the SPI DMA module can be used again.
18.4.4
The SPI DMA engine is enabled and controlled by the
following Special Function Registers:
18.4.4.1
The DMACON1 register is used to select the main
operating mode of the SPI DMA module. The SSCON1
and SSCON0 bits are used to control the slave select
pin.
When MSSP2 is used in SPI Master mode with the SPI
DMA module, SSDMA can be controlled by the DMA
module as an output pin. If MSSP2 will be used to com-
municate with an SPI slave device that needs the SS
pin to be toggled periodically, the SPI DMA hardware
can automatically be used to deassert SS between
each byte, every two bytes or every four bytes.
Alternatively, user firmware can manually generate
slave select signals with normal general purpose I/O
pins, if required by the slave device(s).
When the TXINC bit is set, the TXADDR register will
automatically increment after each transmitted byte.
Automatic transmit address increment can be disabled
by clearing the TXINC bit. If the automatic transmit
address increment is disabled, each byte which is out-
put on SDO2, will be the same (the contents of the
SRAM pointed to by the TXADDR register) for the
entire DMA transaction.
• DMACON1
• TXADDRH
• RXADDRH
• DMABCH
REGISTERS
DMACON1
© 2009 Microchip Technology Inc.
• DMACON2
• TXADDRL
• RXADDRL
• DMABCL