PIC12C672-10I/P Microchip Technology, PIC12C672-10I/P Datasheet - Page 681

• Manufacturer Part Number: PIC12C672-10I/P
• Description: IC MCU OTP 2KX14 A/D 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-10I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 1
• Digital Ic Case Style: DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Glossary
P
Pages
Method of addressing the Program Memory. Midrange devices have 11-bit addressing for
CALL
and
instructions, which gives these instructions a 2-Kword reach. To allow more program
GOTO
memory to be present on a device, program memory is partitioned into contiguous pages, where
each page is 2-Kwords. To select the desired page, the page selection bits (PCLATCH<5:4>)
need to be appropriately configured. Since there are presently 2 page selection bits, 4 pages can
be implemented.
Parallel Slave Port (PSP)
A parallel communication port which is used to interface to a microprocessor’s 8-bit data bus.
POP
A termed used to refer to the action of restoring information from a stack (software and/or hard-
ware). See PUSH.
Postscaler
A circuit that slows the rate of the interrupt generation (or WDT reset) from a counter/timer by
dividing it down.
Power-on Reset POR)
Circuitry which determines if the device voltage rose from a powered down level (0V). If the
device voltage is rising from ground, a device reset occurs and the PWRT is started.
Power-up Timer (PWRT)
A timer which holds the internal reset signal low for a timed delay to allow the device voltage to
reach the valid operating voltage range. Once the timer times out, the OST circuitry is enabled
(for all crystal/resonator device oscillator modes).
Prescaler
A circuit that slows the rate of a clocking source to a counter/timer.
Program Bus
The bus which is used to transfer instruction words form the program memory to the CPU.
Program Counter
A register which specifies the address in program memory that is the next instruction to execute.
Program Memory
Any memory that is one the program memory bus. Static variables may be contained in program
memory (such as tables).
PSP
See Parallel Slave Port.
Pulse Width Modulation (PWM)
A serial signal in which the information is contained in the width of a (high) pulse of a constant
frequency signal. A PWM output, from the CCP module, of the same duty cycle requires no soft-
ware overhead.
PUSH
35
A termed used to refer to the action of saving information onto a stack (software and/or hard-
ware). See POP.
PWM
Pulse Width Modulation.
1997 Microchip Technology Inc.
DS31035A-page 35-9