PIC24FJ48GA002-I/SS Microchip Technology, PIC24FJ48GA002-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC24FJ48GA002-I/SS
• Description: IC PIC MCU FLASH 48K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA002-I/SS

• Core Size: 16-Bit
• Program Memory Size: 48KB (16K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
10. Module: I
DS80470E-page 6
When using I2C1, the SDA1 line state may not be
detected properly unless it is first held low for
150 ns after enabling the I
In Master mode, this error may cause a bus colli-
sion to occur instead of a Start bit transmission.
Transmissions after the SDA1 pin has been held
low will occur correctly.
In Slave mode, the device may not Acknowledge
the first packet sent after enabling the I
In this case, it will return a NACK instead of an
ACK. The device will correctly respond to packets
after detecting a low level on the line for 150 ns.
The I2C2 module operates as expected and does
not exhibit this issue.
Work around
Using an external device or another I/O pin from
the microcontroller, drive the SDA1 pin low.
If no external devices or additional I/O pins are
available, it is sometimes possible to perform the
work around internally, using the following steps:
• With the module in Master mode, configure the
• Clear the LATB9 bit (for the default I2C1
• Enable I2C1 by setting the I2CEN bit
Note that this action could appear to be a Start bit
to an I
pin is not driven low prior to driving RB9/SDA1 low.
It may be necessary to add additional capacitance
to the SDA1 bus in order to maintain the low logic
level long enough for the module to detect the low
logic level. Make sure that when adding capaci-
tance, that the application does not violate the I
timing specifications.
In Slave mode, the I
must either pull the SDAx line low, then high again,
prior to sending the first packet to the device, or
must resend the first packet.
Note that 150 ns is the absolute maximum time
required to avoid the issue. It is possible to work
around the issue using a shorter delay in some
devices.
Affected Silicon Revisions
A3/
A4
RB9 pin as an output.
assignment) or LATB5 (for the alternate I2C1
assignment) to drive the pin low.
(I2C1CON<15>).
X
2
C slave device on the bus if the RB8/SCL1
B4
2
C™ (I2C1, SDA Line State)
B5
B8
2
C master device on the bus
2
C module.
2
C module.
2
C
11. Module: UART
12. Module: UART
13. Module: UART
When the UART is in High-Speed mode, BRGH
(UxMODE<3>) is set; some optimal UxBRG
values can cause reception to fail.
Work around
Test UxBRG values in the application to find a
UxBRG value that works consistently for more
high-speed applications. The user should verify
that the UxBRG baud rate error does not exceed
the
recommended to use a comparable baud rate in
Low-Speed mode.
Affected Silicon Revisions
When the UART is in High-Speed mode
(BRGH = 1),
calculate the baud rate as if it were in Low-Speed
mode.
Work around
The calculated baud rate can be modified by the
following equation:
The user should verify that the baud rate error does
not exceed application limits.
Affected Silicon Revisions
When an auto-baud is detected, the receive inter-
rupt may occur twice. The first interrupt occurs at
the beginning of the Start bit and the second after
reception of the Sync field character.
Work around
If a receive interrupt occurs, check the URXDA bit
(UxSTA<0>) to ensure that valid data is available.
On the first interrupt, no data will be present. The
second interrupt will have the Sync field character
(55h) in the receive FIFO.
Affected Silicon Revisions
A3/
A3/
A3/
A4
A4
A4
X
X
X
New BRG Value = (Auto-Baud BRG + 1) * 4 – 1
application
B4
B4
B4
B5
B5
B5
the
 2010 Microchip Technology Inc.
limits.
B8
B8
B8
auto-baud
If
possible,
sequence
it
can
is