PIC18F26J50-I/SS Microchip Technology, PIC18F26J50-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC18F26J50-I/SS
• Description: IC PIC MCU FLASH 64K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SS

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Interface: EUSART, I2C, SPI, USB
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F46J50 FAMILY
6. Module: Low-Power Modes (Deep Sleep)
EXAMPLE 2:
DS80436C-page 6
EnterDeepSleep:
Entering Deep Sleep mode takes approximately
2 T
events that occur during this Deep Sleep entry
period may not generate a wake-up event.
Work around
If using the RTCC alarm for Deep Sleep wake-up,
code should only enter Deep Sleep mode when
the RTCC Value registers read synchronization bit
(RTCCFG<4>) is clear.
This will prevent missing an RTCC alarm that
could occur during the period after the SLEEP
instruction, but before the Deep Sleep mode has
not been fully entered.
The revision A4 silicon allows insertion of a single
instruction between setting the Deep Sleep Enable
bit (DSEN, DSCONH<7>) and issuing the SLEEP
instruction (see Example 2). The insertion of a NOP
Affected Silicon Revisions
bsf
nop
sleep
(…)
goto
A2
X
CY
, following the SLEEP instruction. Wake-up
A4
DSCONH, DSEN
EnterDeepSleep
DEEP-SLEEP WAKE-UP WORK AROUND
; Enter Deep Sleep mode on SLEEP instruction
; Not compatible with A2 silicon
; Enter Deep Sleep mode
; Add code here to handle wake up events that may
; have been asserted prior to Deep Sleep entry
; re-attempt Deep Sleep entry if desired
instruction before the SLEEP instruction eliminates
the 2 T
missed.
Before using this work around, users should check
their device’s revision ID bits to verify that they
have the A4 silicon. This can be done at run time
by a table read from address, 3FFFFEh.
On revision A2 silicon devices, the instruction can-
not be inserted between setting the DSEN bit and
executing the SLEEP instruction or the device will
enter conventional Sleep mode, not Deep Sleep.
Even on A4 silicon devices, if the firmware imme-
diately executes SLEEP after setting DSEN, the
device will enter Deep Sleep mode without
benefitting from this work around.
CY
window where wake-up events could be
 2010 Microchip Technology Inc.