PIC16F872-I/SO Microchip Technology, PIC16F872-I/SO Datasheet - Page 239

• Manufacturer Part Number: PIC16F872-I/SO
• Description: IC MCU FLASH 2KX14 EE 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.4.1.1
1997 Microchip Technology Inc.
Addressing
Once the SSP module has been enabled, it waits for a START condition to occur. Following the
START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled
with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to
the value of the SSPADD register. The address is compared on the falling edge of the eighth clock
(SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events
occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be received by the slave. The five Most
Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. The R/W bit
(SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For
a 10-bit address the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9 for
slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Table 15-2: Data Transfer Received Byte Actions
Note:Shaded cells show the conditions where the user software did not properly clear the overflow
Transfer is Received
Note:
Status Bits as Data
The SSPSR register value is loaded into the SSPBUF register on the falling edge of the
eight SCL pulse.
The buffer full bit, BF, is set on the falling edge of the eigth SCL pulse.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF, is set (interrupt is generated if enabled) - on the falling edge
of the ninth SCL pulse.
Receive first (high) byte of Address (the SSPIF, BF, and UA (SSPSTAT<1>) bits are set).
Update the SSPADD register with second (low) byte of Address (clears the UA bit and
releases the SCL line).
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
Receive second (low) byte of Address (the SSPIF, BF, and UA bits are set).
Update the SSPADD register with the high byte of Address. This will clear the UA bit and
releases SCL line.
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
Receive repeated START condition.
Receive first (high) byte of Address (the SSPIF and BF bits are set).
Read the SSPBUF register (clears the BF bit) and clear the SSPIF flag bit.
BF
0
1
1
0
condition.
Following the RESTART condition (step 7) in 10-bit mode, the user only needs to
match the first 7-bit address. The user does not update the SSPADD for the second
half of the address.
SSPOV
0
0
1
1
SSPSR
Yes
Yes
No
No
SSPBUF
Section 15. SSP
Generate ACK
Pulse
Yes
No
No
No
(SSP Interrupt occurs
DS31015A-page 15-19
Set bit SSPIF
if enabled)
Yes
Yes
Yes
Yes
15