PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet

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... Any Data Sheet Clarification issues related to the PIC18F6310/6410/8310/8410 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. All of the issues listed here will be addressed in future revisions of the PIC18F6310/6410/8310/8410 silicon. ...

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... PIC18F6310/6410/8310/8410 2. Module: MSSP When the MSSP is configured for SPI Master mode, the SDO pin cannot be disabled by setting the TRISC<5> bit. The SDO pin always outputs the content of SSPBUF regardless of the state of the TRIS bit. In Slave mode with Slave Select enabled, SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the SDO pin can be disabled by placing a logic high level on the SS pin (RF7) ...

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... T1CKPS1:T1CKPS0 bit values. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6310/6410/8310/8410 7. Module: CCP The CCP1 and CCP2 configured for PWM mode, with 1:1 Timer2 prescaler and duty cycle set to the period minus 1, may result in the PWM output(s) bits remaining at a logic low level ...

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... Table 2. Work around Three work arounds exist. 1. Configure the A/D to use the V pins for the voltage references. This is done by setting the VCFG<1:0> bits (ADCON1<5:4>). TABLE 2: A/D CONVERTER CHARACTERISTICS: PIC18F6310/6410/8310/8410 (INDUSTRIAL) Param Symbol Characteristic No. A06A E Offset Error ...

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... TXREGx. Date Codes that pertain to this issue: All engineering and production devices. 12. Module: AUSART The AUSART for PIC18F6310/6410/8310/8410 devices may not recognize a received Stop bit if the combined error rate is too high. Work around 1. Increase the baud rate of the device by decrementing the SPBRGHx:SPBRGx register pair value by one ...

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... PIC18F6310/6410/8310/8410 16. Module: Interrupts If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register ...

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... Microchip Technology Inc. PIC18F6310/6410/8310/8410 The code segment shown in Example 2 demonstrates the work around using the C18 compiler. An optimized C18 version is also pro- vided in Example 3. This example illustrates how it reduces the instruction cycle count from C18 C Compiler, 10 cycles to 3 ...

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... PIC18F6310/6410/8310/8410 17. Module: External Memory Bus (EMB) When the EMB is enabled and configured for 8-bit mode and EBDIS (MEMCON<7>) is clear, the BA0 pin continues to be active during table read and table write operations to internal program memory addresses. Under these conditions, BA0 should be inactive ...

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... SSPOV bit is clear before disabling the module. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6310/6410/8310/8410 26. Module: MSSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1) ...

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... PIC18F6310/6410/8310/8410 27. Module: Timer1 (Asynchronous Counter) When writing to the TMR1H register, under specific conditions possible that the TMR1L register will miss a count while connected to the external oscillator via the T1OSO and T1OSI pins. When Timer1 is started, the circuitry looks for a falling edge before a rising edge can increment the counter. Writing to the TMR1H register is similar to starting Timer1 ...

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... TXREG when timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F6310/6410/8310/8410 29. Module: EUSART/AUSART In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON< ...

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... PIC18F6310/6410/8310/8410 32. Module: Timer1 In 16-Bit Asynchronous Counter mode (with or without use of the Timer1 oscillator), the TMR1H and TMR3H buffers do not update when TMRxL is read. This issue only affects reading the TMRxH regis- ters. The timers increment and set the interrupt flags as expected. The timer registers can also be written as expected ...

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... Power-up Timer (PWRT) gets disabled irrespec- tive of the state of the PWRTEN Configuration bit (CONFIG2L<0>). Work around Do either of the following: © 2007 Microchip Technology Inc. PIC18F6310/6410/8310/8410 1. Enable the BOR using any desired mode and set point BOR operation is not desired: a) Configure the BOR using BOREN<1:0> (CONFIG2L<2:1>). ...

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... PIC18F6310/6410/8310/8410 REVISION HISTORY Rev A Document (8/2004) First revision of this document which includes silicon issues 1-4 (MSSP), 5 (PWM), 6 (CCP), 7 (A/D), 8 (AUSART), 9 (External Memory (Timer1/Timer3) and 11 (Timer1). Rev B Document (02/2005) Updated issues (MSSP), 12 (AUSART) and 14 (Timer1/Timer3) and added issues 6 (CCP), 9 (BOD), 10-11 (EUSART), 15 (Timer1/Timer3) and 16 (Interrupts) ...

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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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