PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet
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... PIC18F6310/6410/8310/8410 64/80-Pin Flash Microcontrollers 2010 Microchip Technology Inc. with nanoWatt XLP Technology Data Sheet DS39635C ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F8310 8K/2M 4096/1M PIC18F8410 16K/2M 8192/1M 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I Master and Slave modes • Addressable USART module: - Supports RS-485 and RS-232 • ...
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... RE0/RD 2 RG0/CCP3 3 RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3 6 RG5/MCLR RG4 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 RE7 is the alternate pin for CCP2 multiplexing Note 1: DS39635C-page PIC18F6310 PIC18F6410 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1 2010 Microchip Technology Inc. ...
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... RG2/RX2/DT2 7 RG3 8 RG5/MCLR RG4 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 RE7 is the alternate pin for CCP2 multiplexing Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F8310 PIC18F8410 RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 56 (1) RB3/INT3/CCP2 55 RB4/KBI0 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 OSC1/CLKI/RA7 49 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 397 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 397 Index .................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 409 Customer Change Notification Service .............................................................................................................................................. 409 Customer Support .............................................................................................................................................................................. 409 Reader Response .............................................................................................................................................................................. 410 PIC18F6310/6410/8310/8410 Product Identification System ............................................................................................................ 411 DS39635C-page 6 2010 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 7 ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 8 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F6310/6410/8310/8410 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F6310/6410/8310/8410 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. ...
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... Like all Microchip PIC18 devices, members of the PIC18F6310/6410/8310/8410 family are available as both standard and low-voltage devices. Standard devices with Flash memory, designated with an “F” in the part number (such as PIC18F6310), accommodate an operating V range of 4.2V to 5.5V. Low-voltage DD parts, designated by “LF” (such as PIC18LF6410), function over an extended V range of 2 ...
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... Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) RESET Instruction, Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 83 with Extended Packages 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F6310 PIC18F6410 DC – 40 MHz DC – 40 MHz 8K 16K 4096 8192 768 768 ...
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... PIC18F6310/6410/8310/8410 FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR 8/16 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode and Control Internal ...
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... RG5 is only available when MCLR functionality is disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. 3: Refer to Section 3.0 “Oscillator Configurations” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Latch 8 8 Data Memory (8/16 Kbytes) Address Latch ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR RG5 MCLR V PP OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Default assignment for CCP2 when Configuration bit, CCP2MX, is set. ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/HLVDIN 27 RA5 AN4 HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0 48 RB0 INT0 RB1/INT1 47 RB1 INT1 RB2/INT2 46 RB2 INT2 RB3/INT3 45 RB3 INT3 RB4/KBI0 44 RB4 KBI0 RB5/KBI1 43 RB5 KBI1 RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD 37 RB7 KBI3 PGD Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 29 RC1 T1OSI (1) CCP2 RC2/CCP1 33 RC2 CCP1 RC3/SCK/SCL 34 RC3 SCK SCL RC4/SDI/SDA 35 RC4 SDI SDA RC5/SDO 36 RC5 SDO RC6/TX1/CK1 31 RC6 TX1 CK1 RC7/RX1/DT1 32 RC7 RX1 ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/PSP0 58 RD0 PSP0 RD1/PSP1 55 RD1 PSP1 RD2/PSP2 54 RD2 PSP2 RD3/PSP3 53 RD3 PSP3 RD4/PSP4 52 RD4 PSP4 RD5/PSP5 51 RD5 PSP5 RD6/PSP6 50 RD6 PSP6 RD7/PSP7 49 RD7 PSP7 Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/RD 2 RE0 RD RE1/WR 1 RE1 WR RE2/CS 64 RE2 CS RE3 63 RE4 62 RE5 61 RE6 60 RE7/CCP2 59 RE7 (2) CCP2 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Default assignment for CCP2 when Configuration bit, CCP2MX, is set. ...
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... PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5 18 RF0 AN5 RF1/AN6/C2OUT 17 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 RF2 AN7 C1OUT RF3/AN8 15 RF3 AN8 RF4/AN9 14 RF4 AN9 RF5/AN10/CV 13 REF RF5 AN10 CV REF RF6/AN11 12 RF6 AN11 RF7/SS 11 RF7 SS Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/CCP3 3 RG0 CCP3 RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3 6 RG4 8 RG5 V 9, 25, 41 10, 26, 38 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR RG5 MCLR V PP OSC1/CLKI/RA7 49 OSC1 CLKI RA7 OSC2/CLKO/RA6 50 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode) ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0 58 RB0 INT0 RB1/INT1 57 RB1 INT1 RB2/INT2 56 RB2 INT2 RB3/INT3/CCP2 55 RB3 INT3 (1) CCP2 RB4/KBI0 54 RB4 KBI0 RB5/KBI1 53 RB5 KBI1 RB6/KBI2/PGC 52 RB6 KBI2 PGC RB7/KBI3/PGD 47 RB7 KBI3 PGD Legend: TTL = TTL compatible input ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/AD0/PSP0 72 RD0 AD0 PSP0 RD1/AD1/PSP1 69 RD1 AD1 PSP1 RD2/AD2/PSP2 68 RD2 AD2 PSP2 RD3/AD3/PSP3 67 RD3 AD3 PSP3 RD4/AD4/PSP4 66 RD4 AD4 PSP4 RD5/AD5/PSP5 65 RD5 AD5 PSP5 RD6/AD6/PSP6 64 RD6 AD6 PSP6 ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5 24 RF0 AN5 RF1/AN6/C2OUT 23 RF1 AN6 C2OUT RF2/AN7/C1OUT 18 RF2 AN7 C1OUT RF3/AN8 17 RF3 AN8 RF4/AN9 16 RF4 AN9 RF5/AN10/CV 15 REF RF5 AN10 CV REF RF6/AN11 14 RF6 AN11 RF7/SS 13 RF7 SS Legend: TTL = TTL compatible input ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RJ0/ALE 62 RJ0 ALE RJ1/OE 61 RJ1 OE RJ2/WRL 60 RJ2 WRL RJ3/WRH 59 RJ3 WRH RJ4/BA0 39 RJ4 BA0 RJ5/CE 40 RJ4 CE RJ6/LB 41 RJ6 LB RJ7/UB 42 RJ7 UB V 11, 31, 51 12, 32, 48 Legend: TTL = TTL compatible input ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F6310/6410/8310/8410 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
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... PIC18F6310/6410/8310/8410 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... PIC18F6310/6410/8310/8410 2.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types PIC18F6310/6410/8310/8410 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F6310/6410/8310/8410 TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... EXT C > EXT 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
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... PIC18F6310/6410/8310/8410 3.6 Internal Oscillator Block The PIC18F6310/6410/8310/8410 devices include an internal oscillator block, which generates two different clock signals; either can be used as the micro- controller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Note 1: Section 3.6.4 “PLL in INTOSC Modes” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F6310/6410/8310/8410 devices are shown in Figure “Special Features of the CPU” for Configuration register details ...
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... Timer1 oscillator starts. 3.7.2 OSCILLATOR TRANSITIONS PIC18F6310/6410/8310/8410 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F6310/6410/8310/8410 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF< ...
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... See Table 5-2 in Note 1: Section 5.0 “Reset” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 44 2010 Microchip Technology Inc. ...
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... POWER-MANAGED MODES PIC18F6310/6410/8310/8410 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Sleep mode • ...
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... PIC18F6310/6410/8310/8410 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... OST OSC PLL 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator Figure 4-2) ...
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... PIC18F6310/6410/8310/8410 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code ...
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... TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 INTOSC Multiplexer OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note 1024 OST OSC PLL 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 n-1 n Clock Transition OST (1) PLL ( n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx) ...
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... Sleep Mode The power-managed Sleep mode PIC18F6310/6410/8310/8410 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (see Figure 4-5) ...
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... Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, T required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set ...
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... PIC18F6310/6410/8310/8410 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS< ...
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... IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 4.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready ...
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... PIC18F6310/6410/8310/8410 TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Before Wake-up Primary Device Clock (PRI_IDLE mode) EC, RC, INTRC (1) T1OSC or INTRC EC, RC, INTRC (3) INTOSC EC, RC, INTRC None (Sleep mode) EC, RC, INTRC In this instance, refers specifically to the 31 kHz INTRC clock source. ...
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... RESET The PIC18F6310/6410/8310/8410 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F6310/6410/8310/8410 REGISTER 5-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-0 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F6310/6410/8310/8410 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.7 “ ...
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... PIC18F6310/6410/8310/8410 5.4 Brown-out Reset (BOR) PIC18F6310/6410/8310/8410 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits. There are a total of four BOR configurations, which are summarized in The BOR threshold is set by the BORV<1:0> bits. If BOR is enabled (any values of BOREN< ...
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... POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) PIC18F6310/6410/8310/8410 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation ...
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... PIC18F6310/6410/8310/8410 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. T PLL 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 , V RISE > PWRT T OST T PWRT T OST ...
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... PIC18F6310/6410/8310/8410 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read ‘0’. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction ...
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... PIC18F6310/6410/8310/8410 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices INDF2 6X10 8X10 POSTINC2 6X10 8X10 POSTDEC2 6X10 8X10 PREINC2 6X10 8X10 PLUSW2 6X10 8X10 FSR2H 6X10 8X10 FSR2L 6X10 8X10 STATUS 6X10 8X10 TMR0H 6X10 8X10 TMR0L 6X10 8X10 ...
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... Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read ‘0’. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction ...
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... PIC18F6310/6410/8310/8410 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices TRISG 6X10 8X10 TRISF 6X10 8X10 TRISE 6X10 8X10 TRISD 6X10 8X10 TRISC 6X10 8X10 TRISB 6X10 8X10 (5) TRISA 6X10 8X10 LATJ 6X10 8X10 LATH 6X10 8X10 LATG 6X10 8X10 ...
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... NOP instruction). The PIC18F6310 and PIC18F8310 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F6410 and PIC18F8410 each have 16 Kbytes of Flash memory and can store up to Section 7 ...
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... Flash memory. Attempts to read above the physical limit of the on-chip Flash (3FFFh) causes a read of all ‘0’s (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6310 and PIC18F6410 devices. REGISTER 6-1: CONFIG3L: CONFIGURATION BYTE REGISTER LOW R/P-1 R/P-1 ...
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... Mode From Microcontroller Yes Extended Yes Microcontroller Microprocessor No Access No Access Microprocessor Yes w/Boot Block 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Extended Microcontroller Mode 000000h (Top of Memory) (Top of Memory 1FFFFFh Microprocessor with Boot Block Mode 000000h 0007FFh 000800h (No (Top of Memory 1FFFFFh Flash ...
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... PIC18F6310/6410/8310/8410 6.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Bit 7 and bit 6 are cleared by user software POR. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
Page 72
... PIC18F6310/6410/8310/8410 6.1.3.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
Page 73
... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 6.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
Page 74
... PIC18F6310/6410/8310/8410 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
Page 75
... GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank” detailed description of the Access RAM. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
Page 76
... PIC18F6310/6410/8310/8410 FIGURE 6-6: DATA MEMORY MAP FOR PIC18F6310/6410/8310/8410 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh DS39635C-page 76 Data Memory Map 000h Access RAM 05Fh 060h ...
Page 77
... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Memory 000h 7 00h Bank 0 ...
Page 78
... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 6-2 TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6310/6410/8310/8410 DEVICES Address Name Address FFFh TOSU ...
Page 79
... TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL (6) STKUNF (6) — PCLATU — — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
Page 80
... PIC18F6310/6410/8310/8410 TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — — (1) RCON IPEN SBOREN — ...
Page 81
... TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRG1 EUSART1 Baud Rate Generator Low Byte RCREG1 EUSART1 Receive Register TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN IPR3 — — RC2IP PIR3 — ...
Page 82
... PIC18F6310/6410/8310/8410 TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH1 EUSART1 Baud Rate Generator High Byte BAUDCON1 ABDOVF RCIDL RXDTP SPBRG2 AUSART2 Baud Rate Generator RCREG2 AUSART2 Receive Register TXREG2 AUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN ...
Page 83
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 intended example, CLRF STATUS, will set the Z bit and leave the remaining Status bits unchanged 6-3, contains (‘ ...
Page 84
... PIC18F6310/6410/8310/8410 6.4 Data Addressing Modes The execution of some instructions in the Note: core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.5 “Data Memory and the Extended Instruction Set” more information. While the program memory can be addressed in only one way – ...
Page 85
... FSR and uses the new value in the operation. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...
Page 86
... PIC18F6310/6410/8310/8410 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory ...
Page 87
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
Page 88
... PIC18F6310/6410/8310/8410 6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
Page 89
... If a table write is being used to write executable code into an external program memory, program instructions will need to be word-aligned. Although it cannot be used in PIC18F6310 Note: devices in normal operation, the TBLWT instruction is still implemented in the instruction set. Executing the instruction takes two instruction cycles, but effectively results in a NOP ...
Page 90
... PIC18F6310/6410/8310/8410 7.2 Control Registers Two control registers are used in conjunction with the TBLRD and TBLWT instructions: the TABLAT register and the TBLPTR register set. 7.2.1 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between the program memory space and data RAM ...
Page 91
... TABLAT, W MOVWF WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Program Memory Space (Odd Byte Address) TBLPTR = xxxxx1 TBLRD ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ; read into TABLAT and increment ...
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... PIC18F6310/6410/8310/8410 7.4 Writing to Program Memory Space (PIC18F8310/8410 only) The table write operation outputs the contents of the TBLPTR and TABLAT registers to the external address and data busses of the external memory interface. Depending on the program memory mode selected, the operation may target any byte address in the device’s memory space ...
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... Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 4 Bit 3 Bit 2 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 94 2010 Microchip Technology Inc. ...
Page 95
... Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate If SBOREN is enabled, its Reset state is ‘1’; otherwise ‘0’. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 As implemented here, the interface is similar to that introduced on PIC18F8X20 microcontrollers. The most notable ...
Page 96
... PIC18F6310/6410/8310/8410 TABLE 8-1: PIC18F8310/8410 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit RD0/AD0/PSP0 PORTD 0 Input/Output or System Bus Address bit 0 or Data bit 0 or Parallel Slave Port bit 0 RD1/AD1/PSP1 PORTD 1 Input/Output or System Bus Address bit 1 or Data bit 1 or Parallel Slave Port bit 1 ...
Page 97
... WRL Note 1: This signal only applies to table writes. See 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 For all 16-bit modes, the Address Latch Enable (ALE) pin indicates that the address bits, A<15:0>, are avail- able on the external memory interface bus. Following the ...
Page 98
... PIC18F6310/6410/8310/8410 8.2.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F8410 devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
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... Note 1: Demultiplexing is only required when multiple memory devices are accessed. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’s BYTE/WORD pin to provide the select signal ...
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... PIC18F6310/6410/8310/8410 8.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 through Figure 8-6. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE Apparent Q ...
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... ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction Execution INST(PC – 2) Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 00h 3AABh 0E55h Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP ...
Page 102
... PIC18F6310/6410/8310/8410 8.3 8-Bit Mode The external memory interface implemented in PIC18F8410 devices operates only in 8-Bit Multiplexed mode; data shares the 8 Least Significant bits of the address bus. Figure 8-1 shows an example of 8-Bit Multiplexed mode for PIC18F8410 devices. This mode is used for a single 8-bit memory connected for 16-bit operation. ...
Page 103
... EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE A<19:16> AD<15:8> AD<7:0> CE ALE OE Opcode Fetch Memory Cycle TBLRD * from 000100h Instruction INST(PC – 2) Execution 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 0Eh 55h 33h Table Read of 92h from 199E67h TBLRD Cycle 2 Q1 ...
Page 104
... PIC18F6310/6410/8310/8410 FIGURE 8-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE 00h A<19:16> AD<15:8> 3Ah AD<7:0> AAh 00h 03h CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the external memory interface. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 If operations in a lower power Run mode are antici- pated, users should provide in their applications for adjusting memory access times at the lower clock speeds ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 106 2010 Microchip Technology Inc. ...
Page 107
... Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 108
... PIC18F6310/6410/8310/8410 Example 9-3 shows the sequence unsigned multiplication. Equation 9-1 algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L RES3:RES0 = (ARG1H ARG2H (ARG1H ARG2L 2 (ARG1L ARG2H 2 (ARG1L ARG2L) ...
Page 109
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices have ...
Page 110
... PIC18F6310/6410/8310/8410 FIGURE 10-1: PIC18F6310/6410/8310/8410 INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<5:4, 0> PIE3<5:4, 0> IPR3<5:4, 0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<5:4, 0> PIE3<5:4, 0> IPR3<5:4, 0> ...
Page 111
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and Note 1: allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 112
... PIC18F6310/6410/8310/8410 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 113
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 INT2IE ...
Page 114
... PIC18F6310/6410/8310/8410 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 115
... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R/W-0 R/W-0 — BCLIF HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 116
... PIC18F6310/6410/8310/8410 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 — — RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: AUSART Receive Interrupt Flag bit 1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read) ...
Page 117
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 TX1IE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 118
... PIC18F6310/6410/8310/8410 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 OSCFIE CMIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
Page 119
... TX2IE: AUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R-0 U-0 U-0 TX2IE — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — ...
Page 120
... PIC18F6310/6410/8310/8410 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R/W-1 R/W-1 — BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 122
... PIC18F6310/6410/8310/8410 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R-1 — — RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: AUSART Receive Priority Flag bit 1 = High priority ...
Page 123
... For details of bit operation, see bit 1 POR: Power-on Reset Status bit For details of bit operation, see bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Register 5-1 ...
Page 124
... PIC18F6310/6410/8310/8410 10.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
Page 125
... Port I/O pins have diode protection to V Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 126
... PIC18F6310/6410/8310/8410 TABLE 11-1: PORTA FUNCTIONS TRIS Pin Name Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/V - RA2 REF 0 1 AN2 REF 1 RA3/AN3/V + RA3 REF 0 1 AN3 REF 1 RA4/T0CKI RA4 0 1 T0CKI x RA5/AN4/HLVDIN RA5 0 1 AN4 1 HLVDIN 1 OSC2/CLKO/RA6 OSC2 ...
Page 127
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 128
... PIC18F6310/6410/8310/8410 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Microprocessor, Extended Note 1: Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only); default assignment is RC1. All other pin functions are disabled when ICSP or ICD operations are enabled. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATB< ...
Page 130
... PIC18F6310/6410/8310/8410 TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB Output Latch Register TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. ...
Page 131
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 On a Power-on Reset, these pins are Note: configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 132
... PIC18F6310/6410/8310/8410 TABLE 11-5: PORTC FUNCTIONS TRIS Pin Name Function Setting RC0/T1OSO/T13CKI RC0 0 1 T1OSO x T13CKI 1 RC1/T1OSI/CCP2 RC1 0 1 T1OSI x (1) CCP2 0 1 RC2/CCP1 RC2 0 1 CCP1 0 1 RC3/SCK/SCL RC3 0 1 SCK 0 1 SCL 0 1 RC4/SDI/SDA RC4 0 1 SDI 1 SDA 1 1 RC5/SDO ...
Page 133
... TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Output Latch Register TRISC PORTC Data Direction Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset Bit 1 Bit 0 Values ...
Page 134
... PIC18F6310/6410/8310/8410 11.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 135
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). External memory interface I/O takes priority over all other digital and PSP I/O. Note 1: Implemented on 80-pin devices only. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATD< ...
Page 136
... PIC18F6310/6410/8310/8410 TABLE 11-7: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RD7/AD7/PSP7 RD7 0 1 (2) AD7 x x PSP7 Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input, Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
Page 137
... PORTE is the high-order byte of the multiplexed address/data bus (AD<15:8>). The TRISE bits are also overridden. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0/AD8/RD, RE1/AD9/WR and RE2/AD10/CS) are configured as digital control inputs for the port ...
Page 138
... PIC18F6310/6410/8310/8410 TABLE 11-9: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/AD8/RD RE0 0 1 (3) AD8 RE1/AD9/WR RE1 0 1 (3) AD9 RE2/AD10/CS RE2 0 1 (3) AD10 RE3/AD11 RE3 0 1 (3) AD11 x x RE4/AD12 RE4 0 1 (3) AD12 x x RE5/AD13 RE5 0 1 (3) AD13 x x RE6/AD14 RE6 0 1 (3) AD14 ...
Page 139
... TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 PORTE RE7 RE6 LATE LATE Output Latch Register TRISE PORTE Data Direction Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 Reset Bit 1 Bit 0 Values ...
Page 140
... PIC18F6310/6410/8310/8410 11.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i ...
Page 141
... CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATF<0> data output; not affected by analog input PORTF<0> data input; disabled when analog input is enabled. ...
Page 142
... PIC18F6310/6410/8310/8410 11.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i ...
Page 143
... TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. RG5 is available as an input only when MCLR is disabled. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATG<0> data output PORTG<0> data input. ...
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... PIC18F6310/6410/8310/8410 11.8 PORTH, LATH and TRISH Registers PORTH is only available Note: PIC18F8310/8410 devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a High-Impedance mode) ...
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... TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 TRISH PORTH Data Direction Register PORTH RH7 RH6 LATH PORTH Output Latch Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATH<0> data output PORTH<0> data input. O DIG External memory interface, Address Line 16. Takes priority over port data ...
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... PIC18F6310/6410/8310/8410 11.9 PORTJ, TRISJ and LATJ Registers PORTJ is available Note: PIC18F8310/8410 devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a High-Impedance mode) ...
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... TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 PORTJ RJ7 RJ6 LATJ LATJ Output Latch Register TRISJ PORTJ Data Direction Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output; takes priority over digital I/O ...
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... PIC18F6310/6410/8310/8410 11.10 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set asynchro- nously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. ...
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... General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — ...
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... PIC18F6310/6410/8310/8410 FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 11-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD Output Latch Register TRISD PORTD Data Direction Register PORTE RE7 RE6 LATE LATE Output Latch Register ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The T0CON register aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in shows a simplified block diagram of the Timer0 module in 16-bit mode ...
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... PIC18F6310/6410/8310/8410 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default, unless a different prescaler value is selected (see “Prescaler”). If the TMR0 Section 12.3 register is written to, the increment is inhibited for the fol- lowing two instruction cycles ...
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... T0CON TMR0ON T08BIT TRISA PORTA Data Direction Register Legend: Shaded cells are not used by Timer0. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. the prescaler 12 ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 154 2010 Microchip Technology Inc. ...
Page 155
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer1 module is shown in Figure operation in Read/Write mode is shown in The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
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... PIC18F6310/6410/8310/8410 13.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM ...
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... T1OSO See the Notes with Table 13-1 Note: information about capacitor selection. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 TABLE 13-1: Osc Type LP Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stabil- ity of the oscillator, but also increases the start-up time ...
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... PIC18F6310/6410/8310/8410 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure located as close as possible to the microcontroller. There should be no circuits passing within the oscillator ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Initialize timekeeping registers ; ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 160 2010 Microchip Technology Inc. ...
Page 161
... Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 162
... PIC18F6310/6410/8310/8410 14.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... Internal clock (F OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer3 module is shown in Figure operation in Read/Write mode is shown in The Timer3 module is controlled through the T3CON register (Register options for the CCP modules (see “ ...
Page 164
... PIC18F6310/6410/8310/8410 15.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous counter • Asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 15-1: TIMER3 BLOCK DIAGRAM ...
Page 165
... RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 166
... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 166 2010 Microchip Technology Inc. ...
Page 167
... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6310/6410/8310/8410 devices have three CCP (Capture/Compare/PWM) modules, labelled CCP1, CCP2 and CCP3. All modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. REGISTER 16-1: CCPxCON: CCP1/CCP2/CCP3 CONTROL REGISTER U-0 U-0 R/W-0 — — DCxB1 bit 7 Legend: ...
Page 168
... PIC18F6310/6410/8310/8410 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 ...
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... Prescaler Q1:Q4 CCP3CON<3:0> CCP3 Pin Prescaler 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. If RC1/CCP2 or RE7/CCP2 is configured Note output, a write to the port can cause a capture condition ...
Page 170
... PIC18F6310/6410/8310/8410 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit, CCP2IE (PIE2<1>), clear to avoid false interrupts and should clear the flag bit, CCP2IF, following any such change in operating mode. 16.2.4 CCP PRESCALER There are four prescaler settings in Capture mode ...
Page 171
... FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM T3CCP2 0 1 T3CCP1 TMR1H TMR1L 0 TMR3H TMR3L 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Special Event Trigger (Timer1/Timer3 Reset) Set CCP1IF Compare Output Comparator Match Logic 4 CCPR1H CCPR1L CCP1CON<3:0> Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) ...
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... PIC18F6310/6410/8310/8410 TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN SBOREN PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP PIR3 — ...
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... Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A PWM output and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
Page 174
... PIC18F6310/6410/8310/8410 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>. The following equation is ...
Page 175
... CCPR3L Capture/Compare/PWM Register 3 (LSB) CCPR3H Capture/Compare/PWM Register 3 (MSB) CCP3CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — RC1IF ...
Page 176
... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 176 2010 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 178
... PIC18F6310/6410/8310/8410 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by Note 1: writing to the SSPBUF register. When enabled, these pins must be properly configured as inputs or outputs. 2: Bit combinations not specifically listed here are either reserved or implemented 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 (2) (3) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
Page 180
... PIC18F6310/6410/8310/8410 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 181
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
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... PIC18F6310/6410/8310/8410 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
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... Interrupt Flag SSPSR to SSPBUF 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), ...
Page 184
... PIC18F6310/6410/8310/8410 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... SSPOV SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.3.10 BUS MODE COMPATIBILITY ...
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... PIC18F6310/6410/8310/8410 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by Note 1: writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C™ MODE) R-0 R-0 R-0 (1) (1) ...
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... PIC18F6310/6410/8310/8410 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 SMP CKE bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz Slew rate control enabled for High-Speed mode (400 kHz) ...
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... Value that will be transmitted when the user initiates an Acknowledge sequence at the end of Note 1: a receive the I C module is not in Idle mode, this bit may not be set (no spooling) and the SSPBUF 2: may not be written (or writes to the SSPBUF are disabled). 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C™ MODE) R/W-0 R/W-0 R/W-0 (1) (2) (2) ...
Page 190
... PIC18F6310/6410/8310/8410 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I operation. Four mode selection bits (SSPCON<3:0>) 2 allow one of the following I C modes to be selected: 2 • Master mode, Clock = (F /4) x (SSPADD + 1) ...
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... CKP (SSPCON<4>). See Section 17.4.4 “Clock for more details. Stretching” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register ...
Page 192
... PIC18F6310/6410/8310/8410 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39635C-page 192 2010 Microchip Technology Inc. ...
Page 193
... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 193 ...
Page 194
... PIC18F6310/6410/8310/8410 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39635C-page 194 2010 Microchip Technology Inc. ...
Page 195
... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 195 ...
Page 196
... PIC18F6310/6410/8310/8410 17.4.4 CLOCK STRETCHING Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
Page 197
... DX SCL CKP WR SSPCON 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the ...
Page 198
... PIC18F6310/6410/8310/8410 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39635C-page 198 2010 Microchip Technology Inc. ...
Page 199
... FIGURE 17-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 199 ...
Page 200
... PIC18F6310/6410/8310/8410 17.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all ...