PIC18F66J93-I/PT Microchip Technology, PIC18F66J93-I/PT Datasheet - Page 36

• Manufacturer Part Number: PIC18F66J93-I/PT
• Description: IC PIC MCU FLASH 64KX4 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J93-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3923 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• Ram Memory Size: 3923Byte
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Digital Ic Case Style: TQFP
• No. Of I/o's: 51
• Embedded Interface Type: AUSART, EUSART, I2C, SPI
• Rohs Compliant: Yes
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.923 B
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 1 x 8 bit, 3 x 16 bit
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

conversion sample. This means the ADRESH:ADRESL
PIC18F87J93 FAMILY
2.5
Figure 2-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 2-4 shows the operation of the A/D converter
after the GO/DONE bit has been set; the ACQT<2:0>
bits are set to ‘010’ and a 4 T
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 2-3:
FIGURE 2-4:
DS39948A-page 34
Note:
(Holding capacitor continues
acquiring input)
AD
Set GO/DONE bit
wait is required before the next acquisition can be
1
T
CY
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D Conversions
T
- T
Automatic
Acquisition
Time
ACQT
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
2
AD
Conversion starts
T
Cycles
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected)
AD
b8
AD
1
3 T
acquisition time is
AD
b7
b9
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
2
4 T
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
AD
b6
b8
3
AD
5 T
AD
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
AD
ADIF bit is set, holding capacitor is reconnected to analog input.
b5
b7
4
6 T
AD
b4
T
5
b6
7 T
AD
Cycles
2.6
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
AD
b3
b5
6
8
T
AD
b2
Use of the CCP2 Trigger
b4
7
9 T
AD
b1
b3
10
8
T
AD
b0
ACQ
ACQ
b2
11
9
© 2009 Microchip Technology Inc.
= 0)
= 4 T
ACQ
10
b1
time is selected before
AD
b0
)
11