PIC24FJ64GA102-I/SO Microchip Technology, PIC24FJ64GA102-I/SO Datasheet - Page 112

• Manufacturer Part Number: PIC24FJ64GA102-I/SO
• Description: IC MCU 16BIT 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GA102-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240020, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, LIN, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA104 FAMILY
9.2.2
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC will
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction or
the first instruction in the ISR.
9.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction (except for Deep Sleep) will be held
off until entry into Sleep or Idle mode has completed.
The device will then wake-up from Sleep or Idle mode.
9.2.4
In PIC24FJ64GA104 family devices, Deep Sleep mode
is intended to provide the lowest levels of power
consumption available, without requiring the use of
external switches to completely remove all power from
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
DS39951C-page 112
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Selective Peripheral Module Control”).
also remain active.
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
DEEP SLEEP MODE
9.2.4.1
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a SLEEP
instruction (PWRSAV #SLEEP_MODE) within one to three
instruction cycles to minimize the chance that Deep
Sleep will be spuriously entered.
If the PWRSAV command is not given within three
instruction cycles, the DSEN bit will be cleared by the
hardware and must be set again by the software before
entering Deep Sleep mode. The DSEN bit is also
automatically cleared when exiting the Deep Sleep
mode.
The sequence to enter Deep Sleep mode is:
1.
2.
3.
4.
5.
6.
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
Note:
Note:
If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see
Section 9.2.4.7
details).
If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (CW4<6>).
If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module (see Section 19.0 “Real-Time
Clock and Calendar (RTCC)” for more
information).
If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
Enter Deep Sleep mode by immediately issuing
a PWRSAV #0 instruction.
Since Deep Sleep mode powers down the
microcontroller by turning off the on-chip
V
capability is available only when operating
with the internal regulator enabled.
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T
after clearing the RELEASE bit.
DDCORE
Entering Deep Sleep Mode
voltage regulator, Deep Sleep
“Deep
 2010 Microchip Technology Inc.
Sleep
WDT”
for
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