PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 13

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

37. Module: External Memory Bus
38. Module: External Memory Bus
39. Module: Power-up Timer
© 2007 Microchip Technology Inc.
For PIC18F8XXX devices, the Stack Pointer may
incorrectly increment during a table read operation
if the external memory bus wait states are enabled
(i.e.,
(CONFIG3L<7>
(MEMCON<5:4>) are not equal to ‘11’).
Work around
If using the external memory bus and performing
TBLRD operations with a non-zero wait state
(CONFIG3L<7>
(MEMCON<5:4>) are not equal to ‘11’), disable
interrupts by clearing the GIE/GIEH (INTCON<7>)
and PEIE/GIEL (INTCON<6>) bits prior to
executing any TBLRD operation.
Date Codes that pertain to this issue:
All engineering and production devices.
The A19:A16 address lines may release to their
inactive states at the same time as Read/Write bus
control pins (OE, WRH and WRL). This violates
bus timing condition described in Figure 26.5 and
Figure 26.6 of the data sheet. The result may be a
device on the memory bus detecting an address
change when a Read or Write is initiated.
This situation may be more likely to affect faster
peripheral memory devices (e.g., Flash RAMs).
Longer propagation delays on the control signal
lines, which can be influenced by stray capaci-
tance and other factors, are more likely to
adversely affect the situation.
Work around
Two workarounds are presented here. Others may
be available.
1. Use a hardware latch, triggered by falling
2. Add a delay circuit on the A19:A16 address
Date Codes that pertain to this issue:
All engineering and production devices.
If Brown-out Reset (BOR) is disabled, then the
Power-up Timer (PWRT) gets disabled irrespec-
tive of the state of the PWRTEN Configuration bit
(CONFIG2L<0>).
Work around
Do either of the following:
edges on the ALE signal, on the A19:A16
address lines. This will hold the address until
WRL or WRH can transition to an inactive
state.
lines to extend the valid time for the signals.
Configuration
=
=
bit,
0)
0
and
and
WAIT,
WAIT
WAIT<1:0>
is
PIC18F6310/6410/8310/8410
clear
bits
40. Module: Analog-to-Digital (A/D)
1. Enable the BOR using any desired mode and
2. If BOR operation is not desired:
Date Codes that pertain to this issue:
All engineering and production devices.
When the A/D clock source is selected as 2 T
or RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 T
8 T
selecting the 2 T
Date Codes that pertain to this issue:
All engineering and production devices.
OSC
set point.
a) Configure the BOR using
b) Configure the BOR for the lowest voltage
c) When code execution begins following
, 16 T
BOREN<1:0> = 01 (CONFIG2L<2:1>).
BOR is controlled by SBOREN.
set point by clearing the BORV<1:0> bits
(CONFIG2L<4:3>).
In this configuration, the SBOREN bit
resets to ‘1’, enabling the BOR.
all Resets, disable the BOR by clearing
the SBOREN bit (RCON<6>).
Converter Module
OSC
DL
OSC
(Differential Linearity Error) may
, 32 T
or RC modes.
OSC
or 64 T
IL
(Integral Linearity
DS80206F-page 13
OSC
) and avoid
OSC
OSC
,