PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet

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... SS RB6/PGC PGC RB7/PGD PGD Legend Input Output Power Note 1: All power supply (V ) and ground (V DD © 2007 Microchip Technology Inc. Family Flash MCUs 2.1 Hardware Requirements In High-Voltage programming PIC18F8410/8490/8493 family devices require two programmable power supplies: one for V • PIC18F6393 MCLR/V ...

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... RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3 6 RG5/MCLR RG4 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT Note 1: RE7 is the alternate pin for CCP2 multiplexing. DS39624C-page PIC18F6X10 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1 33 © 2007 Microchip Technology Inc. ...

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... RG0/CCP3 5 RG1/TX2/CK2 6 RG2/RX2/DT2 7 RG3 8 RG5/MCLR RG4 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 Note 1: RE7 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc PIC18F8X10 RJ2/WRL 60 RJ3/WRH 59 RB0/INT0/FLT0 58 RB1/INT1 57 RB2/INT2 56 (1) RB3/INT3/CCP2 55 RB4/KBI0 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 OSC1/CLKI/RA7 49 V ...

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... RG3/SEG27 6 RG5/MCLR RG4/SEG26 RF7/SS/SEG25 11 RF6/AN11/SEG24 12 RF5/AN10/CV /SEG23 REF 13 RF4/AN9/SEG22 14 RF3/AN8/SEG21 15 RF2/AN7/C1OUT/SEG20 16 Note 1: RE7 is the alternate pin for CCP2 multiplexing. DS39624C-page PIC18F6X90 PIC18F6X93 RB0/INT0 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9 46 RB3/INT3/SEG10 45 RB4/KBI0/SEG11 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO/SEG12 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1/SEG13 © 2007 Microchip Technology Inc. ...

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... RG1/TX2/CK2/SEG29 6 RG2/RX2/DT2/SEG28 7 RG3/SEG27 8 RG5/MCLR RG4/SEG26 RF7/SS/SEG25 13 RF6/AN11/SEG24 14 RF5/AN10/CV /SEG23 REF 15 RF4/AN9/SEG22 16 RF3/AN8/SEG21 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: RE7 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc PIC18F8X90 PIC18F8X93 RJ2/SEG34 60 RJ3/SEG35 59 RB0/INT0 58 RB1/INT1/SEG8 57 RB2/INT2/SEG9 56 RB3/INT3/SEG10 55 RB4/KBI0/SEG11 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 OSC1/CLKI/RA7 ...

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... TBLPTRH, at RAM address 0FF7h • TBLPTRL, at RAM address 0FF6h TBLPTRU Addr[21:16] The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write operations. described in Section 5.0 TBLPTRH TBLPTRL Addr[15:8] Addr[7:0] © 2007 Microchip Technology Inc. ...

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... Block 0 001FFFh Unimplemented Read as ‘0’ 200000h 200007h 300000h 30000Dh 3FFFFEh 3FFFFFh Note: Sizes of memory areas are not to scale. © 2007 Microchip Technology Inc. Code Memory User ID Space Configuration Bits Space Device ID Space ID Location 1 200000h ID Location 2 200001h ID Location 3 200002h ID Location 4 200003h ...

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... ID Location 8 200007h CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h CONFIG3L 300004h CONFIG3H 300005h CONFIG4L 300006h CONFIG4H 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh © 2007 Microchip Technology Inc. ...

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... FIGURE 2-7: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P12 P1 D110 MCLR PGD PGC PGD = Input © 2007 Microchip Technology Inc. FIGURE 2-8: bits are then Yes Program Memory Program IDs Verify Program Verify IDs Configuration Bits Configuration Bits HIGH-LEVEL PROGRAMMING FLOW Start ...

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... Data Payload PGD = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-Bit Command © 2007 Microchip Technology Inc. ...

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... Verified? Yes Note 1: The erased state of configuration bits are given in Table 5-2. © 2007 Microchip Technology Inc. A “Blank” or “Erased” memory cell will read as a ‘1’. So, “Blank Checking” a device merely means to verify that all bytes read as FFh, except the configuration bits. ...

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... Write 8Ah TO 3C0004h to erase device NOP Hold PGD low until erase completes. CHIP ERASE FLOW Start Load Address Pointer to 3C0004h Write 018Ah to Erase Device Delay P11 + P10 Time Done P10 P11 16-Bit Erase Time Data Payload © 2007 Microchip Technology Inc. ...

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... TBLPTR<3:0> TBLPTR<3:0> TBLPTR<3:0> TBLPTR<3:0> TBLPTR<3:0> TBLPTR<3:0> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. © 2007 Microchip Technology Inc. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. The code sequence PIC18F8410/8490/8493 family device is shown in Table 3-3 ...

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... Start LoopCount = 0 Configure Device for Writes Addr = 16 x LoopCount Load 16 Bytes to Write Buffer at <Addr> Start Programming Sequence Delay P9 + P10 Time (Hold PGC High for P9 Time and PGC Low for P10 Time) All No Locations Done? Yes Done © 2007 Microchip Technology Inc. ...

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... F8 0000 0E 00 0000 6E F7 0000 0E 00 0000 6E F6 1101 <LSB><MSB> 1101 <LSB><MSB> 1101 <LSB><MSB> 1111 <LSB><MSB> 0000 00 00 © 2007 Microchip Technology Inc P5A 16-Bit Data Payload 4-Bit Command PGD = Input Table 3-4 demonstrates the code sequence required to write the ID locations ...

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... NOP - hold PGC high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 Hold PGC High for a to program two consecutive Start Load Odd Configuration Address Program MSB P9 Time Done © 2007 Microchip Technology Inc. ...

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... PGD = Input © 2007 Microchip Technology Inc. The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output ...

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... Section 4.1 “Read Code Memory, ID Locations and Configuration Bits” for implementation details of reading configuration data. Set Pointer = 200000h Read Low Byte Read High Byte No Failure, Word = Expect Report Error No Does No Failure, Data? Report Error Yes All ID Locations Verified? Yes Done © 2007 Microchip Technology Inc. ...

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... PIC18F6493 PIC18F8410 PIC18F8490 PIC18F8493 Note: The ‘x’s in DEVID1 contain the device revision code. © 2007 Microchip Technology Inc 0Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. 5.2 Device ID Word The device ID word for the PIC18F8410/8490/8493 family is located at 3FFFFEh:3FFFFFh ...

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... BOREN0 PWRTEN ---1 1111 WDTPS0 WDTEN ---1 1111 PM1 PM0 11-- --11 — CCP2MX 1--- -0-1 — STVREN 10-- ---1 — CP ---- ---1 — — ---- ---- — — ---- ---- — — ---- ---- — EBTR ---- ---1 — — ---- ---- REV1 REV0 1xxx xxxx DEV4 DEV3 0000 xxxx © 2007 Microchip Technology Inc. ...

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... BORV1:BORV0 CONFIG2L WDTEN CONFIG2H Note 1: Unimplemented in PIC18F8410/8490/8493 family devices; maintain the default unprogrammed value. © 2007 Microchip Technology Inc. Description Oscillator Selection bits 1111 = External RC oscillator w/ OSC2 configured as ‘divide by 4 clock output’ 1110 = External RC oscillator w/ OSC2 configured as ‘divide by 4 clock output’ ...

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... MCLR pin enabled, RG5 disabled 0 = RG5 input pin enabled, MCLR disabled Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow/Underflow will cause Reset 0 = Stack Overflow/Underflow will not cause Reset Enhanced CPU Enable bit 1 = Enhanced CPU enabled 0 = Enhanced CPU disabled ( Microprocessor w/ © 2007 Microchip Technology Inc. ...

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... DEV2:DEV0 DEVID1 REV4:REV0 DEVID1 Note 1: Unimplemented in PIC18F8410/8490/8493 family devices; maintain the default unprogrammed value. © 2007 Microchip Technology Inc. Description Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger enabled Code Protection bit (code memory area 0000h-3FFFh for PIC18FX410/X490/X493 devices and 0000h-1FFFh for ...

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... Configuration Word information may be provided. When embedding Configuration Word information in the Hex file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 5-4 CHECKSUM COMPUTATION Code ...

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... HS/PLL mode only) + 1.5 μs (for EC mode only) where T is the Instruction Cycle Time For specific values, refer to the Electrical Characteristics section of the Device Data Sheet for the particular device. © 2007 Microchip Technology Inc. Min Max Units ...

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... PIC18F8410/8490/8493 FAMILY NOTES: DS39624C-page 26 © 2007 Microchip Technology Inc. ...

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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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