PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 6

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F8410/8490/8493 FAMILY
2.3
The code memory space extends from 000000h to
001FFFh
PIC18FX310/X390/X393 devices and from 000000h to
003FFFh
PIC18FX410/X490/X493 devices.
TABLE 2-2
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through table reads and table
writes (in ICSP mode). Their locations in the memory
map are shown in Figure 2-5.
Users may store identification information (user ID) in
eight ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
DS39624C-page 6
PIC18F6310
PIC18F8310
PIC18F6390
PIC18F6393
PIC18F8390
PIC18F8393
PIC18F6410
PIC18F8410
PIC18F6490
PIC18F6493
PIC18F8490
PIC18F8493
Device
Memory Map
(16
(8 Kbytes)
Kbytes)
IMPLEMENTATION OF CODE
MEMORY
Code Memory Size (Bytes)
in
000000h-003FFFh (16K)
000000h-001FFFh (8K)
in
a
a
single
single
block
block
for
for
Locations 300000h through 30000Dh are reserved for
the configuration bits. These bits select various device
options
“Configuration Word”. These configuration bits read
out normally, even after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits are read-only bits. These bits
may be used by the programmer to identify what device
type is being programmed and are described in
Section 5.0 “Configuration Word”. These device ID
bits read out normally, even after code protection.
2.3.1
Memory in the address space 0000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
Addr[21:16]
TBLPTRU
and
MEMORY ADDRESS POINTER
are
Addr[15:8]
TBLPTRH
© 2007 Microchip Technology Inc.
described
in
TBLPTRL
Addr[7:0]
Section 5.0