DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 6

• Manufacturer Part Number: DSPIC33FJ16GS502-I/SO
• Description: IC DSPIC MCU/DSP 16K 28-SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5. Module: PWM
DS80439H-page 6
When
Complementary, Redundant and Push-pull output
modes, with Independent Time Base (ITB = 1) and
Independent Fault mode (IFLTMOD = 1) enabled,
the PWMxH and PWMxL outputs should be
affected by the Fault and Current Limit events as
follows:
• PWMxH is affected by Current-Limit source
• PWMxL is affected by Fault source (FCL-
On silicon revisions affected by this erratum, the
Current-Limit event works correctly for the PWMxH
pin. However, the Fault event is reset by the
secondary local time base although it is not used to
generate the time base value. As a result, the fault
event on PWMxL pin may not work as expected.
This erratum only applies to the cycle-by-cycle Fault
mode (FLTMOD = 0b01).
Work around
If PWM is in Complementary, Redundant or Push-
Pull mode and (ITB = 1), set SPHASEx to have the
same value as PHASEx. This will ensure that the
Fault event on the PWMxL pin is reset at the start
of the new PWM period for cycle-by-cycle
independent fault operation.
Affected Silicon Revisions
A2
(FCLCON<CLSRC>) and the Current-Limit
should be reset at the end of the primary local
time base.
CON<FLTSRC>) and the Fault should be reset
at the end of the primary local time base.
X
A3
X
PWM
A4
X
module
is
operated
in
6. Module: PWM
7. Module: PWM
8. Module: PWM
The independent time base PWM outputs may not
be synchronized with the Master time base PWM
outputs
simultaneously.
Work around
To synchronize the Independent PWM outputs
with the Master time base PWM outputs, disable
the Immediate Updates bit (IUE = 0), ensure that
the three Least Significant bits of the period are
zero, and that the duty cycle is between 8 ns and
the period minus 0x8.
This work around will not work if the frequency of
the PWM module is being updated on the fly.
Affected Silicon Revisions
In PWM Latched Fault mode, the PWM outputs
may be latched on both the rising as well as the
falling edge of the Fault signal, regardless of the
fault input polarity selection (set with the
FCLCONx<FLTPOL> bit setting).
Work around
None.
Affected Silicon Revisions
A bit write to the CLMOD bit (bit 8) in the
FCLCONx register or consecutive writes to the
lower byte and higher byte of the FCLCONx
register, causes all other bits of the high byte to be
loaded with zeros.
Work around
Use Word writes for the FCLCONx register instead
of bit or byte writes.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
when
A4
A4
A4
X
X
X
© 2010 Microchip Technology Inc.
both
modes
are
used