DSPIC33FJ64GP306A-I/PT Microchip Technology, DSPIC33FJ64GP306A-I/PT Datasheet - Page 88

• Manufacturer Part Number: DSPIC33FJ64GP306A-I/PT
• Description: IC DSPIC MCU/DSP 64K 64-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP306A-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 64KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJXXXGPX06A/X08A/X10A
TABLE 6-1:
6.1
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
TABLE 6-2:
DS70593B-page 88
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note:
Reset Type
WDTR
MCLR
SWR
POR
BOR
Clock Source Selection at Reset
All Reset flag bits may be set or cleared by the user software.
Flag Bit
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
RESET FLAG BIT OPERATION
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
OSCILLATOR SELECTION VS
Clock Source Determinant
Trap conflict event
Illegal opcode or uninitialized
W register access
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
BOR, POR
POR
Preliminary
Setting Event
6.2
The Reset times for various types of device Reset are
summarized in Table 6-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Device Reset Times
—
POR, BOR
POR, BOR
POR
POR, BOR
PWRSAV instruction, POR, BOR
POR, BOR
POR, BOR
—
 2009 Microchip Technology Inc.
Clearing Event