DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet - Page 231

• Manufacturer Part Number: DSPIC30F6012A-30I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012A30IP

I
I/O Pin Specifications
I/O Ports .............................................................................. 63
I
I
I
I
I
I
Idle Current (I
In-Circuit Debugger (ICD 2) .............................................. 160
In-Circuit Serial Programming (ICSP) ......................... 51, 143
Initialization Condition for RCON Register Case 1 ........... 157
Initialization Condition for RCON Register Case 2 ........... 157
Input Capture (CAPX) Timing Characteristics .................. 194
Input Capture Module ......................................................... 83
Input Capture Operation During Sleep and Idle Modes ...... 84
Input Capture Timing Requirements ................................. 194
Input Change Notification Module ....................................... 67
© 2006 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 97
C 7-bit Slave Mode Operation .......................................... 97
C Master Mode Operation ................................................ 99
C Master Mode Support ................................................... 99
C Module .......................................................................... 95
S Mode Operation .......................................................... 131
Input .......................................................................... 181
Output ....................................................................... 181
Parallel (PIO) .............................................................. 63
Reception.................................................................... 98
Transmission............................................................... 97
Reception.................................................................... 97
Transmission............................................................... 97
Baud Rate Generator................................................ 100
Clock Arbitration........................................................ 100
Multi-Master Communication, Bus Collision and
Reception.................................................................... 99
Transmission............................................................... 99
Addresses ................................................................... 97
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 99
Interrupts..................................................................... 98
IPMI Support ............................................................... 99
Operating Function Description .................................. 95
Operation During CPU Sleep and Idle Modes .......... 100
Pin Configuration ........................................................ 95
Programmer’s Model................................................... 95
Register Map............................................................. 101
Registers..................................................................... 95
Slope Control .............................................................. 99
Software Controlled Clock Stretching
Various Modes ............................................................ 95
Data Justification....................................................... 131
Frame and Data Word Length Selection................... 131
Interrupts..................................................................... 84
Register Map............................................................... 85
CPU Idle Mode............................................................ 84
CPU Sleep Mode ........................................................ 84
Register Map for dsPIC30F6011A/6012 A
Register Map for dsPIC30F6011A/6012A
Bus Arbitration .................................................. 100
Master Mode ..................................................... 205
Slave Mode ....................................................... 207
Master Mode ..................................................... 206
Slave Mode ....................................................... 208
Master Mode ..................................................... 205
Slave Mode ....................................................... 207
(STREN = 1) ....................................................... 98
(Bits 7-0) ............................................................. 67
(Bits 15-8) ........................................................... 67
IDLE
) ............................................................ 178
dsPIC30F6011A/6012A/6013A/6014A
Preliminary
Instruction Addressing Modes ............................................ 39
Instruction Set
Internet Address ............................................................... 233
Interrupt Controller
Interrupt Priority .................................................................. 46
Interrupt Sequence ............................................................. 48
Interrupts ............................................................................ 45
L
Load Conditions................................................................ 184
Low Voltage Detect (LVD) ................................................ 158
Low-Voltage Detect Characteristics.................................. 181
LVDL Characteristics ........................................................ 182
M
Memory Organization 1, 9, 15, 25, 39, 45, 51, 57, 63, 69, 73,
Microchip Internet Web Site.............................................. 233
Modes of Operation
Module ................................................................................ 95
Modulo Addressing ............................................................. 40
MPLAB ASM30 Assembler, Linker, Librarian ................... 172
MPLAB ICD 2 In-Circuit Debugger ................................... 173
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment
MPLAB PM3 Device Programmer .................................... 173
MPLINK Object Linker/MPLIB Object Librarian ................ 172
N
NVM
Register Map for dsPIC30F6013A/6014A
Register Map for dsPIC30F6013A/6014A
File Register Instructions ............................................ 39
Fundamental Modes Supported ................................. 39
MAC Instructions ........................................................ 40
MCU Instructions ........................................................ 39
Move and Accumulator Instructions ........................... 40
Other Instructions ....................................................... 40
Overview................................................................... 166
Summary .................................................................. 163
Register Map .............................................................. 50
Interrupt Stack Frame................................................. 49
79, 83, 87, 91, 95, 103, 111, 123, 133, 163
Core Register Map ..................................................... 37
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback .................................................................. 113
Normal Operation ..................................................... 113
Applicability................................................................. 42
Operation Example..................................................... 41
Start and End Address ............................................... 41
W Address Register Selection.................................... 41
In-Circuit Emulator.................................................... 173
In-Circuit Emulator.................................................... 173
Software ................................................................... 171
Register Map .............................................................. 55
(Bits 15-8) ........................................................... 67
(Bits 7-0) ............................................................. 67
DS70143C-page 229