C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 299

IC 8051 MCU 32K FLASH 32-QFP

C8051F560-IQ

Manufacturer Part Number
C8051F560-IQ
Description
IC 8051 MCU 32K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Datasheets

Specifications of C8051F560-IQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1693

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F560-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F560-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 27.1.
The configuration in Figure 27.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only. 
Additional resistors may be necessary depending on the specific application.
Output (c)
RST (a)
Input (b)
Figure 27.1. Typical C2 Pin Sharing
C2 Interface Master
Rev. 1.1
C2CK
C2D
C8051Fxxx
C8051F55x/56x/57x
299

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