C8051F366-GQ Silicon Laboratories Inc, C8051F366-GQ Datasheet - Page 287

• Manufacturer Part Number: C8051F366-GQ
• Description: IC 8051 MCU 32K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F366-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1648

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Revision 0.1 to Revision 0.2
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Revision 0.2 to Revision 1.0
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Updated specification tables with most recently available characterization data.
Fixed an error with the SYSCLK specification in Table 3.1, “Global Electrical Characteristics,” on
page 33.
Corrected the name of the PMAT bit in SFR Definition 10.2. IP: Interrupt Priority.
Corrected the reset value for SFR Definition 22.2. PCA0MD: PCA0 Mode.
Updated specification tables with characterization data.
Fixed Table 1.1, “Product Selection Guide,” on page 19 to reflect the correct number of Port I/O pins
for the C8051F361/2/4/5.
Updated Section “10. Interrupt Handler” on page 107.
Updated SFR Definition 11.1
Updated SFR Definition 15.2.
Added Table 16.2, “Internal Low Frequency Oscillator Electrical Characteristics,” on page 172.
Updated SFR Definition 16.9:
Added Table 19.7 and Table 19.8 on page 233 for UART Baud Rates when using the PLL.
Updated Table 22.1, “PCA Timebase Input Options,” on page 265:
Added Revision B to “Revision Specific Behavior” on page 281.
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Added note describing EA change behavior when followed by single cycle instruction.
Changed the MAC0SC (MAC0CF.5) bit description to correctly refer to the MAC0SD bit.
Changed the EMI0CF description to properly describe the 1k XRAM boundaries.
Specified that the undefined states for PLLLP3–0 are RESERVED.
Specified that the undefined states of CPS2–0 are RESERVED.
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