C8051F34B-GQ Silicon Laboratories Inc, C8051F34B-GQ Datasheet - Page 61

• Manufacturer Part Number: C8051F34B-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F34B-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• On-chip Adc: 17-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1534

Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown
in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by
the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see
to ‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
(Programmed with CP0HYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CP0-
CP0+
VIN+
VIN-
Disabled
V
OL
Figure 7.2. Comparator Hysteresis Plot
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
V
OH
+
_
CP0
Section “9.3. Interrupt Handler” on page
Positive Hysteresis
Maximum
OUT
Rev. 1.3
Negative Hysteresis
Disabled
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
88.) The CPnFIF flag is set
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