C8051F005-GQ Silicon Laboratories Inc, C8051F005-GQ Datasheet - Page 139

IC 8051 MCU 32K FLASH 64TQFP

C8051F005-GQ

Manufacturer Part Number
C8051F005-GQ
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F00xr
Datasheets

Specifications of C8051F005-GQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
2304Byte
Cpu Speed
25MHz
No. Of Timers
4
No. Of Pwm Channels
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1188 - DEV KIT FOR F005/006/007
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1187

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0
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is 0 or the input signal /INT0 is
logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal /INT0,
facilitating pulse width measurements.
Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value before
enabling the timer.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer
1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.
19.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers
are enabled and configured in Mode 1 in the same manner as for Mode 0.
139
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SYSCLK
/INT0
T0
GATE0
TR0
Crossbar
Crossbar
12
TR0
0
1
0
1
1
1
X = Don’t Care
Figure 19.1. T0 Mode 0 Block Diagram
CKCON
M
T
2
0
1
M
T
1
GATE0
M
T
0
X
0
1
1
G
A
T
E
1
Rev. 1.7
C
T
/INT0
1
/
M
T
1
1
TMOD
X
X
0
1
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
Counter/Timer
TL0
Disabled
Disabled
Enabled
Enabled
(8 bits)
TH0
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt

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