M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 275

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R
R
M
e
E
1
. v
J
6
Figure 16.3 S00 and S20 Registers
0
C
2
9
0 .
2 /
B
0
0
8
0
4
G
J
7
a
I C 0 D a t a S h i f t R e g i s t e r
I
o r
NOTES:
2
0 -
b 7
2
. n
b7
C0 Clock Control Register
u
2
1. Write is enabled only when the ES0 bit in the S1D0 register is "1". Because the same register is used for both
3
b 6
p
0
b6
, 1
0
storing transmit/receive data, write the transmit data after the receive data is read out. When the S00 register
is set, the BC2 to BC0 bits in the S1D0 register are set to "000
register are set to "0".
(
M
b 5
b5
2
0
1
0
b 4
b4
6
7
C
b 3
b3
2 /
page 253
, 8
b 2
b2
M
b 1
b1
1
6
b 0
b0
C
Transmit/receive data are stored.
In master transmit mode, the start condition/stop condition are triggered by
writing data to the register (refer to 16.9 START Condition Generation
Method and 16.11 STOP Condition Generation Method). Start transmitting
or receiving data, synchronized with S
f o
2 /
Bit Symbol
ACK-CLK
ACKBIT
8
MODE
3
CCR0
CCR1
CCR2
CCR3
CCR4
FAST
) B
8
5
Symbol
S00
Symbol
S20
S
S
ACK Bit
ACK Clock Bit
CL
CL
Frequency Control Bits
Mode Specification Bit
Bit Name
Address
02E0
16
Function
02E4
Address
CL
2
.
" and the LRB, AAS and AL bits in the S10
16
16. MULTI-MASTER I
See Table 16.3
0: Standard clock mode
1: High-speed clock mode
0: ACK is returned
1: ACK is not returned
0: No ACK clock
1: With ACK clock
After Reset
XX
16
Function
After Reset
00
16
2
C bus INTERFACE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)