KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part NumberR0K561622S000BE
DescriptionKIT STARTER FOR H8SX/1622
ManufacturerRenesas Electronics America
SeriesRenesas Starter Kits (RSK)
TypeMCU
R0K561622S000BE datasheets
 

Specifications of R0K561622S000BE

ContentsBoard, Cables, CD, Debugger, Power SupplySilicon ManufacturerRenesas
FeaturesCoding And Debugging, E10A Emulator, RS232 Serial ConnectionKit ContentsBoard
Silicon Family NameH8SX/1622FSilicon Core NumberR5F61622N50LGV
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With/related ProductsH8SX/1622
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Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website:
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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st
April 1
, 2010
Renesas Electronics Corporation

R0K561622S000BE Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    H8SX/1622 Group 32 Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change ...

  • Page 4

    Rev. 2.00 Sep. 16, 2009 Page ii of xxviii ...

  • Page 5

    This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

  • Page 6

    General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

  • Page 7

    Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users ...

  • Page 8

    Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...

  • Page 9

    Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...

  • Page 10

    Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator DTC Data transfer controller INTC Interrupt controller PPG Programmable pulse generator SCI ...

  • Page 11

    Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.1.1 Applications .......................................................................................................... 1 1.1.2 Overview of Functions.......................................................................................... 2 1.2 List of Products..................................................................................................................... 8 1.3 Block Diagram...................................................................................................................... 9 1.4 Pin Descriptions.................................................................................................................. 10 1.4.1 Pin Assignments ................................................................................................. 10 1.4.2 Pin Assignment for Each Operating Mode ...

  • Page 12

    Addressing Modes and Effective Address Calculation....................................................... 59 2.8.1 Register Direct—Rn ........................................................................................... 59 2.8.2 Register Indirect—@ERn................................................................................... 60 2.8.3 Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) ...................................................................................................... 60 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), ...

  • Page 13

    Reset Status Register (RSTSR)........................................................................... 81 4.3.2 Reset Control/Status Register (RSTCSR)........................................................... 82 4.4 Pin Reset ............................................................................................................................. 83 4.5 Deep Software Standby Reset............................................................................................. 83 4.6 Watchdog Timer Reset ....................................................................................................... 83 4.7 Determination of Reset Generation Source......................................................................... 83 Section 5 Exception Handling ...

  • Page 14

    Interrupt Sources............................................................................................................... 120 6.4.1 External Interrupts ............................................................................................ 120 6.4.2 Internal Interrupts ............................................................................................. 121 6.5 Interrupt Exception Handling Vector Table...................................................................... 122 6.6 Interrupt Control Modes and Interrupt Operation............................................................. 127 6.6.1 Interrupt Control Mode 0.................................................................................. 127 6.6.2 Interrupt Control Mode 2.................................................................................. ...

  • Page 15

    Idle Control Register (IDLCR) ......................................................................... 170 8.2.7 Bus Control Register 1 (BCR1) ........................................................................ 172 8.2.8 Bus Control Register 2 (BCR2) ........................................................................ 174 8.2.9 Endian Control Register (ENDIANCR)............................................................ 175 8.2.10 SRAM Mode Control Register (SRAMCR) ..................................................... 176 8.2.11 Burst ROM ...

  • Page 16

    Extension of Chip Select (CS) Assertion Period............................................... 227 8.9 Address/Data Multiplexed I/O Interface........................................................................... 228 8.9.1 Address/Data Multiplexed I/O Space Setting ................................................... 228 8.9.2 Address/Data Multiplex.................................................................................... 228 8.9.3 Data Bus ........................................................................................................... 228 8.9.4 I/O Pins Used for Address/Data Multiplexed I/O ...

  • Page 17

    DMA Address Control Register (DACR) ......................................................... 278 9.3.8 DMA Module Request Select Register (DMRSR) ........................................... 284 9.4 Transfer Modes ................................................................................................................. 285 9.5 Operations......................................................................................................................... 286 9.5.1 Address Modes ................................................................................................. 286 9.5.2 Transfer Modes ................................................................................................. 290 9.5.3 Activation Sources............................................................................................ 295 9.5.4 ...

  • Page 18

    Operation .......................................................................................................................... 355 10.5.1 Bus Cycle Division ........................................................................................... 357 10.5.2 Transfer Information Read Skip Function ........................................................ 359 10.5.3 Transfer Information Writeback Skip Function................................................ 360 10.5.4 Normal Transfer Mode ..................................................................................... 360 10.5.5 Repeat Transfer Mode ...................................................................................... 361 10.5.6 Block Transfer ...

  • Page 19

    Port 2................................................................................................................. 395 11.2.3 Port 3................................................................................................................. 399 11.2.4 Port 5................................................................................................................. 404 11.2.5 Port 6................................................................................................................. 405 11.2.6 Port A................................................................................................................ 408 11.2.7 Port D................................................................................................................ 412 11.2.8 Port E ................................................................................................................ 412 11.2.9 Port F ................................................................................................................ 414 11.2.10 Port H................................................................................................................ 417 11.2.11 Port ...

  • Page 20

    Buffer Operation............................................................................................... 488 12.4.4 Cascaded Operation .......................................................................................... 492 12.4.5 PWM Modes..................................................................................................... 494 12.4.6 Phase Counting Mode....................................................................................... 500 12.5 Interrupt Sources............................................................................................................... 506 12.6 DTC Activation ................................................................................................................ 509 12.7 DMAC Activation ............................................................................................................ 509 12.8 A/D Converter Activation................................................................................................. 509 12.9 Operation Timing.............................................................................................................. ...

  • Page 21

    Non-Overlapping Pulse Output......................................................................... 545 13.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ........................... 547 13.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output)........... 548 13.4.7 Inverted Pulse Output ....................................................................................... 550 13.4.8 Pulse Output Triggered by ...

  • Page 22

    Conflict between TCOR Write and Compare Match........................................ 584 14.8.5 Conflict between Compare Matches A and B................................................... 585 14.8.6 Switching of Internal Clocks and TCNT Operation ......................................... 585 14.8.7 Mode Setting with Cascaded Connection ......................................................... 587 14.8.8 Module Stop Function ...

  • Page 23

    Serial Extended Mode Register_2 (SEMR_2) .................................................. 635 16.4 Operation in Asynchronous Mode .................................................................................... 637 16.4.1 Data Transfer Format........................................................................................ 638 16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ......................................................................................... 639 16.4.3 Clock................................................................................................................. 640 16.4.4 SCI Initialization (Asynchronous ...

  • Page 24

    Section Bus Interface 2 (IIC2)................................................................ 681 17.1 Features............................................................................................................................. 681 17.2 Input/Output Pins.............................................................................................................. 683 17.3 Register Descriptions........................................................................................................ 684 2 17.3 Bus Control Register A (ICCRA) ............................................................... 685 2 17.3 Bus Control Register B ...

  • Page 25

    Single Mode...................................................................................................... 723 18.4.2 Scan Mode ........................................................................................................ 725 18.4.3 Input Sampling and A/D Conversion Time ...................................................... 727 18.4.4 External Trigger Input Timing.......................................................................... 729 18.5 Interrupt Source ................................................................................................................ 730 18.6 A/D Conversion Accuracy Definitions ............................................................................. 730 18.7 Usage Notes ...................................................................................................................... ...

  • Page 26

    DSE Bit............................................................................................................. 768 Section 20 D/A Converter ................................................................................. 769 20.1 Features............................................................................................................................. 769 20.2 Input/Output Pins.............................................................................................................. 770 20.3 Register Descriptions........................................................................................................ 770 20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 770 20.3.2 D/A Control Register 01 (DACR01) ................................................................ 771 ...

  • Page 27

    Section 23 Clock Pulse Generator .....................................................................869 23.1 Register Description ......................................................................................................... 871 23.1.1 System Clock Control Register (SCKCR) ........................................................ 871 23.1.2 ∆Σ A/D Mode Register (DSADMR)................................................................. 874 23.2 Oscillator........................................................................................................................... 875 23.2.1 Connecting Crystal Resonator .......................................................................... 875 23.2.2 External Clock Input ......................................................................................... ...

  • Page 28

    Deep Software Standby Mode .......................................................................................... 908 24.8.1 Entry to Deep Software Standby Mode ............................................................ 908 24.8.2 Exit from Deep Software Standby Mode.......................................................... 909 24.8.3 Pin State on Exit from Deep Software Standby Mode...................................... 910 24.8.4 Bφ Operation after Exit ...

  • Page 29

    Flash Memory Characteristics ........................................................................................ 1012 Appendix............................................................................................................1013 A. Port States in Each Pin State........................................................................................... 1013 B. Product Lineup................................................................................................................ 1018 C. Package Dimensions ....................................................................................................... 1019 D. Treatment of Unused Pins............................................................................................... 1021 Example of an External Circuit of ∆Σ A/D Converter.................................................... 1024 ...

  • Page 30

    Rev. 2.00 Sep. 16, 2009 Page xxviii of xxviii ...

  • Page 31

    Features The core of each product in the H8SX/1622 Group of CISC (complex instruction set computer) microcomputers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original ...

  • Page 32

    Section 1 Overview 1.1.2 Overview of Functions Table 1.1 gives an overview of the functions of the H8SX/1622 Group products. Table 1.1 Overview of Functions Module/ Classification Function Memory ROM RAM CPU CPU Operating mode Rev. 2.00 Sep. 16, 2009 ...

  • Page 33

    Module/ Classification Function CPU MCU operating mode Interrupt Interrupt (sources) controller (INTC) Break interrupt (UBC) Description Mode 1: User boot mode (selected by driving the MD2 and MD1 pins low and driving the MD0 pin high) Mode 2: Boot mode ...

  • Page 34

    Section 1 Overview Module/ Classification Function DMA DMA controller (DMAC) Data transfer controller (DTC) External bus Bus extension controller (BSC) Rev. 2.00 Sep. 16, 2009 Page 4 of 1036 REJ09B0414-0200 Description • Two-channel DMA transfer available • Three activation methods ...

  • Page 35

    Module/ Classification Function Clock Clock pulse generator (CPG) A/D converter 10-bit A/D converter (ADC) 16-bit ∆Σ A/D converter (∆Σ AD) Description • One clock generation circuit available • Separate clock signals are provided for each of functional modules (detailed below) ...

  • Page 36

    Section 1 Overview Module/ Classification Function D/A converter D/A converter (DAC) Timer 8-bit timer (TMR) 16-bit timer pulse unit (TPU) Program- mable pulse generator (PPG) Watchdog timer Watchdog timer (WDT) Serial interface Serial communi- cation interface (SCI) Smart card/ SIM ...

  • Page 37

    Module/ Classification Function bus interface I C bus interface 2 (IIC2) I/O ports Package Operating frequency/ Power supply voltage Operating ambient temperature (°C) Description • Two channels • Bus can be directly driven (the SCL and ...

  • Page 38

    Section 1 Overview 1.2 List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product part No. Table 1.2 List of Products Product Part No. ROM Capacity R5F61622N50FPV 256 Kbytes R5F61622N50LGV 256 ...

  • Page 39

    Block Diagram RAM ROM H8SX CPU DTC Clock pulse generator External bus [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller WDT: Watchdog timer WDT TMR (unit 0) × 2 channels TMR (unit ...

  • Page 40

    Section 1 Overview 1.4 Pin Descriptions 1.4.1 Pin Assignments AVccP AVrefT AVrefB AVccA ANDS4N ANDS1 B AVssP P41 AVssA ANDS5P ANDS2 C P42 P40 P43 REXT ANDS4P ANDS0 E P47 P44 ...

  • Page 41

    P62/TMO2/SCK4/IRQ10-B/TRST 109 PLLVcc 110 P63/TMRI3/IRQ11-B/TMS 111 PLLVss 112 P64/TMCI3/IRQ12-B/TDI 113 P65/TMO3/IRQ13-B/TCK 114 Vcc 115 NMI 116 MD0 117 P50/AN0/IRQ0-B 118 ...

  • Page 42

    Section 1 Overview 1.4.2 Pin Assignment for Each Operating Mode Table1.3 Pin Assignment for Each Operating Mode Pin No. LQFP LGA Modes P40 4 ...

  • Page 43

    Pin No. LQFP LGA Modes PF4/A20 PF3/A19 30 K2 PF2/A18 31 J3 PF1/A17 32 K1 PF0/A16 33 L2 PE7/A15 34 K3 PE6/A14 35 L1 PE5/A13 36 M1 PE4/A12 ...

  • Page 44

    Section 1 Overview Pin No. LQFP LGA Modes P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/ IRQ12 P25/PO5/TIOCA4/TMCI1/RxD1/IRQ13 P26/PO6/TIOCA5/TMO1/TxD1/IRQ14 59 L7 P27/PO7/TIOCA5/TIOCB5/IRQ15 60 K9 P17/ANDSTRG/IRQ7-A/TCLKD-B/SCL0 P16/SCK3/DACK1-A/IRQ6-A/TCLKC-B/SDA0 ...

  • Page 45

    Pin No. LQFP LGA Modes H12 PI4/D12/TMO4 86 H10 PI5/D13/TMO5 87 J13 PI6/D14/TMO6 88 H11 G12 PI7/D15/TMO7 90 G10 P37/PO15/TIOCA2/TIOCB2/TCLKD-A RES 91 H13 92 F12 P36/PO14/TIOCA2 93 G13 P35/PO13/TIOCA1/TIOCB1/TCLKC-A/ DACK1-B 94 G11 ...

  • Page 46

    Section 1 Overview Pin No. LQFP LGA Modes 112 B12 PLLV SS 113 A11 P64/TMCI3/IRQ12-B/TDI 114 C11 P65/TMO3/IRQ13-B/TCK 115 B10 V CC 116 C10 NMI 117 A10 MD0 118 B9 P50/AN0/IRQ0-B 119 C9 P51/AN1/IRQ1-B 120 B8 ...

  • Page 47

    Pin No. LQFP LGA Modes 141 142 C4 REXT 143 ref 144 ref E5 NC Section 1 Overview Pin Name Modes 4 and ...

  • Page 48

    Section 1 Overview 1.4.3 Pin Functions Table 1.4 Pin Functions Classification Pin Name Power supply PLLV CC PLLV SS Clock XTAL EXTAL Bφ Operating mode MD2 to MD0 control RES System control STBY EMLE ...

  • Page 49

    Classification Pin Name BACK Bus control BS-A/BS RD/WR LHWR LLWR LUB LLB CS0 CS1 CS2-A/CS2-B CS3 CS4 CS5-A/CS5-B CS6-A/CS6-B CS7-A/CS7-B WAIT I/O Description Output Bus acknowledge signal, which indicates that the bus has been released. Output Indicates ...

  • Page 50

    Section 1 Overview Classification Pin Name Interrupt NMI IRQ15 IRQ14 IRQ13-A/IRQ13-B IRQ12-A/IRQ12-B IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DREQ0-A/DREQ0-B DMA controller DREQ1-A/DREQ1-B (DMAC) DACK0-A/DACK0-B DACK1-A/DACK1-B TEND0-A/TEND0-B TEND1-A/TEND1-B 16-bit timer TCLKA-A/TCLKA-B pulse unit (TPU) TCLKB-A/TCLKB-B ...

  • Page 51

    Classification Pin Name 16-bit timer TIOCA2 pulse unit (TPU) TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Programmable PO15 to PO0 pulse generator (PPG) 8-bit timer TMO0 to TMO7 (TMR) TMCI0 to TMCI3 TMRI0 to TMRI3 WDTOVF Watchdog timer ...

  • Page 52

    Section 1 Overview Classification Pin Name A/D converter AN7 to AN0 ADTRG0 D/A converter DA1 DA0 A/D converter D/A converter AV SS Vref ∆Σ A/D ANDS5N converter ANDS5P ANDS4N ANDS4P ANDS3 ANDS2 ANDS1 ANDS0 ANDSTRG ...

  • Page 53

    Classification Pin Name ∆Σ A/D AVCM converter REXT I/O ports P17 to P10 P27 to P20 P37 to P30 P47 to P40 P57 to P50 P65 to P60 PA7 PA6 to PA0 PD7 to ...

  • Page 54

    Section 1 Overview Rev. 2.00 Sep. 16, 2009 Page 24 of 1036 REJ09B0414-0200 ...

  • Page 55

    The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...

  • Page 56

    Section 2 CPU • Two base registers  Vector base register  Short address base register • 4-Gbyte address space  Program: 4 Gbytes  Data: 4 Gbytes • High-speed operation  All frequently-used instructions executed in one or two ...

  • Page 57

    CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. These modes can be selected by the mode pins of this LSI. CPU operating modes 2.2.1 Normal Mode The exception vector table and ...

  • Page 58

    Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...

  • Page 59

    Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...

  • Page 60

    Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...

  • Page 61

    Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...

  • Page 62

    Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...

  • Page 63

    Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...

  • Page 64

    Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...

  • Page 65

    General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...

  • Page 66

    Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. SP (ER7) 2.5.2 Program Counter (PC) ...

  • Page 67

    Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can ...

  • Page 68

    Section 2 CPU Initial Bit Bit Name Value 2 Z Undefined R Undefined R Undefined R/W 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask ...

  • Page 69

    Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for ...

  • Page 70

    Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...

  • Page 71

    Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...

  • Page 72

    Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...

  • Page 73

    Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 5 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword size Notes: 1. ...

  • Page 74

    Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L ...

  • Page 75

    Classifi- cation Instruction Size Arithmetic MULXS, B/W operations DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B MAC — CLRMAC — LDMAC — STMAC — Logic AND, OR, XOR B operations B B W/L NOT B W/L ...

  • Page 76

    Section 2 CPU Classifi- cation Instruction Size Bit BFLD B manipu- BFST B lation 8 Branch BRA/BS, BRA/BC BSR/BS, BSR/BC* B System LDC B/W* control (CCR, EXR) LDC L (VBR, SBR) STC B/W* (CCR, EXR) STC L (VBR, ...

  • Page 77

    Table 2.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size — Branch BRA/BS, BRA/BC — BSR/BS, BSR/BC — Bcc — BRA — BRA/S — JMP — BSR — JSR — RTS, RTS/L — System TRAPA control — ...

  • Page 78

    Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...

  • Page 79

    Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE → (EAs) MOVTPE* B @SP+ → Rn POP W/L ...

  • Page 80

    Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...

  • Page 81

    Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...

  • Page 82

    Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVU W/L Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient bits ÷ 32 bits → 32-bit quotient. ...

  • Page 83

    Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) AND B/W/L Performs a logical AND operation on data between immediate data, general registers, and memory. (EAd) ∨ #IMM → (EAd), (EAd) ...

  • Page 84

    Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...

  • Page 85

    Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR B ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in ...

  • Page 86

    Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...

  • Page 87

    Table 2.11 System Control Instructions Instruction Size Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. RTE/L — Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP — Causes ...

  • Page 88

    Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...

  • Page 89

    Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...

  • Page 90

    Section 2 CPU 2.8.2 Register Indirect—@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In ...

  • Page 91

    Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− • Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ...

  • Page 92

    Section 2 CPU Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is ...

  • Page 93

    Immediate—#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate ...

  • Page 94

    Section 2 CPU 2.8.10 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed 8-bit absolute address in ...

  • Page 95

    Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of ...

  • Page 96

    Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...

  • Page 97

    Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...

  • Page 98

    Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state ...

  • Page 99

    Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has six operating modes (modes and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. Table 3.1 lists ...

  • Page 100

    Section 3 MCU Operating Modes Modes are external extended modes, in which the external memory and devices can be accessed. In the external extended modes, the external address space can be designated as 8-bit or 16-bit address ...

  • Page 101

    Bit Bit Name Initial Value R/W     MDS3 Undefined* 10 MDS2 Undefined* 9 MDS1 Undefined* 8 MDS0 Undefined*  7 Undefined*    ...

  • Page 102

    Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit 15 14  ...

  • Page 103

    Initial Bit Bit Name Value  10 Undefined 9 EXPE Undefined 8 RAME 1  All 0 1 DTCMD 1  Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. 2. ...

  • Page 104

    Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the ...

  • Page 105

    Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access ...

  • Page 106

    Section 3 MCU Operating Modes 3.3.7 Pin Functions Table 3.3 lists the pin functions in each operating mode. Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode) Port Mode 1 Port A PA7 P*/C PA6 to PA3 P*/C PA2 ...

  • Page 107

    Mode 1 User boot mode (Advanced mode) H'000000 On-chip ROM H'040000 External address space reserved area * * H'FD9000 Access prohibited area H'FDC000 External address space reserved area * * H'FF0000 Access prohibited area External H'FF2000 ...

  • Page 108

    Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FF0000 Access prohibited area H'FF2000 External address space/ reserved area * H'FF6000 On-chip RAM/ ...

  • Page 109

    Types of Resets There are three types of resets: a pin reset, deep software standby reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized by a reset. Figure ...

  • Page 110

    Section 4 Resets Note that some registers are not initialized by any of the resets. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses ...

  • Page 111

    Register Descriptions This LSI has the following registers for resets. • Reset status register (RSTSR) • Reset control/status register (RSTCSR) 4.3.1 Reset Status Register (RSTSR) RSTSR indicates a source for generating an internal reset. Bit 7 6  Bit ...

  • Page 112

    Section 4 Resets 4.3.2 Reset Control/Status Register (RSTCSR) RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. RSTCSR is initialized to H’ pin reset or a deep software standby ...

  • Page 113

    Pin Reset This is a reset generated by the RES pin. When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to firmly reset the LSI, ...

  • Page 114

    Section 4 Resets Reset exception handling RSTCSR.RSTE = 1 & RSTCSR.WOVF = 1 Yes Watchdog timer reset Figure 4.2 Example of Reset Generation Source Determination Flow Rev. 2.00 Sep. 16, 2009 Page 84 of 1036 REJ09B0414-0200 No No RSTSR. DPSRSTF=1 ...

  • Page 115

    Section 5 Exception Handling 5.1 Exception Handling Types and Priority As table 5.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and an illegal instruction (general illegal instruction or slot ...

  • Page 116

    Section 5 Exception Handling 5.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...

  • Page 117

    Exception Source Reserved for system use User area (open space) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. ...

  • Page 118

    Section 5 Exception Handling Table 5.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + ...

  • Page 119

    Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral ...

  • Page 120

    Section 5 Exception Handling 5.3.3 On-Chip Peripheral Functions after Reset Release After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF, respectively, and all modules except the DTC and DMAC enter module stop mode. Consequently, ...

  • Page 121

    Bφ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2)(4)) ...

  • Page 122

    Section 5 Exception Handling 5.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit ...

  • Page 123

    Address Error 5.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 5.5 may cause an address error. Table 5.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description Instruction CPU Fetches instructions ...

  • Page 124

    Section 5 Exception Handling 5.5.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as ...

  • Page 125

    Interrupts 5.6.1 Interrupt Sources Interrupt sources are NMI, UBC break interrupt, IRQ0 to IRQ15, and on-chip peripheral modules, as shown in table 5.7. Table 5.7 Interrupt Sources Type Source NMI NMI pin (external input) UBC break User break controller ...

  • Page 126

    Section 5 Exception Handling 5.6.2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign eight priority/mask levels to interrupts other than NMI to enable multiple-interrupt control. The source ...

  • Page 127

    Instruction Exception Handling There are two instructions that cause exception handling: trap instruction and illegal instruction. 5.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all ...

  • Page 128

    Section 5 Exception Handling 5.7.2 Sleep Instruction The exception handling starts when a sleep instruction (SLEEP) is executed while the SSBY bit in SBYCR is clear (= 0) and the SLPIE bit in SBYCR is set (= 1). The exception ...

  • Page 129

    Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction starts when a ...

  • Page 130

    Section 5 Exception Handling 5.8 Stack Status after Exception Handling Figure 5.3 shows the stack after completion of exception handling. Advanced mode SP Interrupt control mode 0 Note: * Ignored on return. Figure 5.3 Stack Status after Exception Handling Rev. ...

  • Page 131

    Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer ...

  • Page 132

    Section 5 Exception Handling Rev. 2.00 Sep. 16, 2009 Page 102 of 1036 REJ09B0414-0200 ...

  • Page 133

    Section 6 Interrupt Controller 6.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...

  • Page 134

    Section 6 Interrupt Controller A block diagram of the interrupt controller is shown in figure 6.1. INTCR NMIEG NMI input NMI input unit IRQ inputs IRQ input unit ISCR Internal interrupt sources Source selector WOVI to DSADI DTCER [Legend] Interrupt ...

  • Page 135

    Input/Output Pins Table 6.1 shows the pin configuration of the interrupt controller. Table 6.1 Pin Configuration Name I/O NMI Input IRQ15 to IRQ0 Input 6.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...

  • Page 136

    Section 6 Interrupt Controller 6.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7 6   Bit Name Initial Value Initial Bit Bit Name Value ...

  • Page 137

    CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC and DMAC transfer. The ...

  • Page 138

    Section 6 Interrupt Controller Initial Bit Bit Name Value 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. ...

  • Page 139

    Interrupt Priority Registers (IPRA to IPRI, IPRK, IPRL, IPRP to IPRR) IPR sets priory (levels for interrupts other than NMI. Setting a value in the range from B'000 ...

  • Page 140

    Section 6 Interrupt Controller Initial Bit Bit Name Value 10 IPR10 1 9 IPR9 1 8 IPR8 1  IPR6 1 5 IPR5 1 4 IPR4 1  IPR2 1 1 IPR1 1 0 ...

  • Page 141

    IRQ Enable Register (IER) IER enables interrupt requests IRQ15 to IRQ0. However, the bits of this register cannot set the IRQ interrupt requests (IRQ3 to IRQ0) to exit from deep software standby mode. For details, see section 24.2.6, Deep ...

  • Page 142

    Section 6 Interrupt Controller Initial Bit Bit Name Value 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 Note: The bits of this register cannot set the IRQ ...

  • Page 143

    IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request from IRQ15 to IRQ0 input. Upon changing the setting of ISCR, IRQnF ( 15) in ISR ...

  • Page 144

    Section 6 Interrupt Controller • ISCRH Initial Bit Bit Name Value 15 IRQ15SR 0 14 IRQ15SF 0 13 IRQ14SR 0 12 IRQ14SF 0 11 IRQ13SR 0 10 IRQ13SF 0 9 IRQ12SR 0 8 IRQ12SF 0 Rev. 2.00 Sep. 16, 2009 ...

  • Page 145

    Initial Bit Bit Name Value 7 IRQ11SR 0 6 IRQ11SF 0 5 IRQ10SR 0 4 IRQ10SF 0 3 IRQ9SR 0 2 IRQ9SF 0 1 IRQ8SR 0 0 IRQ8SF 0 R/W Description R/W IRQ11 Sense Control Rise R/W IRQ11 Sense Control ...

  • Page 146

    Section 6 Interrupt Controller • ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 11 IRQ5SR 0 10 IRQ5SF 0 9 IRQ4SR 0 8 IRQ4SF 0 Rev. 2.00 Sep. 16, 2009 ...

  • Page 147

    Initial Bit Bit Name Value 7 IRQ3SR 0 6 IRQ3SF 0 5 IRQ2SR 0 4 IRQ2SF 0 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 Note: The bits of this register cannot set the edge selections ...

  • Page 148

    Section 6 Interrupt Controller 6.3.6 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request register. However, the bits of this register cannot set the IRQ interrupt request flags, IRQnF ( 0), to exit from ...

  • Page 149

    Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ interrupt used to leave software standby mode. The IRQ interrupt used to leave software standby mode should not be set as the DTC activation source. Bit 15 14 ...

  • Page 150

    Section 6 Interrupt Controller 6.4 Interrupt Sources 6.4.1 External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to leave software standby mode. For the external interrupt to exit from deep software standby ...

  • Page 151

    Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not ...

  • Page 152

    Section 6 Interrupt Controller 6.5 Interrupt Exception Handling Vector Table Table 6.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control ...

  • Page 153

    Classification Interrupt Source  Reserved for system use TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V TPU_4 TGI4A TGI4B TCI4V TCI4U Vector Address Vector Offset* Number ...

  • Page 154

    Section 6 Interrupt Controller Classification Interrupt Source TPU_5 TGI5A TGI5B TCI5V TCI5U  Reserved for system use TMR_0 CMI0A CMI0B OV0I TMR_1 CMI1A CMI1B OV1I TMR_2 CMI2A CMI2B OV2I TMR_3 CMI3A CMI3B OV3I DMAC DMTEND0 DMTEND1 Reserved for system use ...

  • Page 155

    Classification Interrupt Source  Reserved for system use SCI_0 ERI0 RXI0 TXI0 TEI0 SCI_1 ERI1 RXI1 TXI1 TEI1 SCI_2 ERI2 RXI2 TXI2 TEI2 SCI_3 ERI3 RXI3 TXI3 TEI3 SCI_4 ERI4 RXI4 TXI4 TEI4  Reserved for system use TMR_4 CMI4A ...

  • Page 156

    Section 6 Interrupt Controller Classification Interrupt Source TMR_5 CMI5A CMI5B OV5I TMR_6 CMI6A CMI6B OV6I TMR_7 CMI7A CMI7B OV7I  Reserved for system use IIC2 IICI0 Reserved for system use IICI1 Reserved for system use A/D ADI0 Reserved for system ...

  • Page 157

    Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by ...

  • Page 158

    Section 6 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure ...

  • Page 159

    Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and the IPR setting. There are eight levels ...

  • Page 160

    Section 6 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 6.4 Flowchart of Procedure Up to Interrupt Acceptance Rev. 2.00 Sep. 16, 2009 Page 130 of 1036 REJ09B0414-0200 Program execution state No Interrupt generated? Yes ...

  • Page 161

    Interrupt Exception Handling Sequence Figure 6.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip ...

  • Page 162

    Section 6 Interrupt Controller 6.6.4 Interrupt Response Times Table 6.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used ...

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    Table 6.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation [Legend] m: Number of wait cycles in an external device access. 6.6.5 ...

  • Page 164

    Section 6 Interrupt Controller Interrupt request On-chip peripheral Interrupt request module clear signal Interrupt request IRQ Interrupt request clear signal interrupt Interrupt controller Figure 6.6 Block Diagram of DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Sources The activation ...

  • Page 165

    Priority Determination The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt Sources, DTC Vector Addresses, and ...

  • Page 166

    Section 6 Interrupt Controller 6.7 CPU Priority Control Function Over DTC and DMAC The interrupt controller has a function to control the priority among the DTC, DMAC, and the CPU by assigning different priority levels to the DTC, DMAC, and ...

  • Page 167

    The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 ...

  • Page 168

    Section 6 Interrupt Controller Table 6.8 shows a setting example of the priority control function over the DTC and DMAC and the transfer request control state. A priority level can be independently set to each DMAC channel, but the table ...

  • Page 169

    Usage Notes 6.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to ...

  • Page 170

    Section 6 Interrupt Controller 6.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is ...

  • Page 171

    Interrupts of Peripheral Modules To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This makes the request signal ...

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    Section 6 Interrupt Controller Rev. 2.00 Sep. 16, 2009 Page 142 of 1036 REJ09B0414-0200 ...

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    Section 7 User Break Controller (UBC) The user break controller (UBC) generates a UBC break interrupt request each time the state of the program counter matches a specified break condition. The UBC break interrupt is a non- maskable interrupt and ...

  • Page 174

    Section 7 User Break Controller (UBC) 7.2 Block Diagram Instruction execution pointer Module stop Mode control BARAH BARAL Break address Break BARBH BARBL control BARCH BARCL BARDH BARDL BRCRA BRCRB BRCRC BRCRD [Legend] BARAH, BARAL: Break address register A BARBH, ...

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    Register Descriptions Table 7.1 lists the register configuration of the UBC. Table 7.1 Register Configuration Register Name Break address register A Break address mask register A Break address register B Break address mask register B Break address register C ...

  • Page 176

    Section 7 User Break Controller (UBC) 7.3.1 Break Address Register n (BARA, BARB, BARC, BARD) Each break address register n (BARn) consists of break address register nH (BARnH) and break address register nL (BARnL). Together, BARnH and BARnL specify the ...

  • Page 177

    Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) Be sure to write H'FF00 0000 to break address mask register n (BAMRn). Operation is not guaranteed if another value is written here. BAMRnH Bit BAMRn31 ...

  • Page 178

    Section 7 User Break Controller (UBC) 7.3.3 Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels and D of the UBC ...

  • Page 179

    Initial Bit Bit Name Value 5 IDn1 0 4 IDn0 0 3 RWn1 0 2 RWn0 0   [Legend Channels Section 7 User Break Controller (UBC) R/W Description R/W Break ...

  • Page 180

    Section 7 User Break Controller (UBC) 7.4 Operation The UBC does not detect condition matches in standby states (sleep mode, all-module clock stop mode, software standby, deep software standby, and hardware standby modes). 7.4.1 Setting of Break Control Conditions 1. ...

  • Page 181

    Condition Match Flag Condition match flags are set when the break conditions match. The condition match flags of the UBC are listed in table 7.2. Table 7.2 List of Condition Match Flags Register Flag Bit BRCRA CMFCPA (bit 13) ...

  • Page 182

    Section 7 User Break Controller (UBC) 7.5 Usage Notes 1. PC break usage note  Contention between a SLEEP instruction (to place the chip in the sleep state or on software standby) and PC break If a break before a ...

  • Page 183

    CKS Register read The value read retained Register write Flag bit Flag bit is set to 1 Figure 7.3 Flag Bit Clearing Sequence (Condition Match Flag) 4. The valid range of break addresses in the MCU and ...

  • Page 184

    Section 7 User Break Controller (UBC) Rev. 2.00 Sep. 16, 2009 Page 154 of 1036 REJ09B0414-0200 ...

  • Page 185

    Section 8 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus ...

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    Section 8 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be ...

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    A block diagram of the bus controller is shown in figure 8.1. CPU address bus DMAC address bus DTC address bus Internal bus control signals CPU bus mastership acknowledge signal DTC bus mastership acknowledge signal DMAC bus mastership acknowledge signal ...

  • Page 188

    Section 8 Bus Controller (BSC) 8.2 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • ...

  • Page 189

    Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit 15 14 Bit Name ABWH7 ABWH6 Initial Value 1 1 R/W R/W R/W Bit 7 6 Bit Name ABWL7 ...

  • Page 190

    Section 8 Bus Controller (BSC) 8.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit 15 14 Bit Name AST7 ...

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    Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA Bit 15 14  Bit Name W72 Initial Value 0 1 ...

  • Page 192

    Section 8 Bus Controller (BSC) • WTCRA Initial Bit Bit Name Value  W72 1 13 W71 1 12 W70 1  W62 1 9 W61 1 8 W60 1  Rev. ...

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    Initial Bit Bit Name Value 6 W52 1 5 W51 1 4 W50 1  W42 1 1 W41 1 0 W40 1 R/W Description R/W Area 5 Wait Control R/W These bits select ...

  • Page 194

    Section 8 Bus Controller (BSC) • WTCRB Initial Bit Bit Name Value  W32 1 13 W31 1 12 W30 1  W22 1 9 W21 1 8 W20 1  Rev. ...

  • Page 195

    Initial Bit Bit Name Value 6 W12 1 5 W11 1 4 W10 1  W02 1 1 W01 1 0 W00 1 R/W Description R/W Area 1 Wait Control R/W These bits select ...

  • Page 196

    Section 8 Bus Controller (BSC) 8.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O ...

  • Page 197

    Bφ RD RDNn = 0 Data RD RDNn = 1 Data Figure 8.2 Read Strobe Negation Timing (Example of 3-State Access Space) CS Assertion Period Control Registers (CSACR) 8.2.5 CSACR selects whether or not the assertion periods of the chip ...

  • Page 198

    Section 8 Bus Controller (BSC) Initial Bit Bit Name Value 15 CSXH7 0 14 CSXH6 0 13 CSXH5 0 12 CSXH4 0 11 CSXH3 0 10 CSXH2 0 9 CSXH1 0 8 CSXH0 0 7 CSXT7 0 6 CSXT6 0 ...

  • Page 199

    T Bφ Address CSn AS BS RD/WR RD Read Data bus LHWR, LLWR Write Data bus Figure 8.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0) Bus cycle T T ...

  • Page 200

    Section 8 Bus Controller (BSC) 8.2.6 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and the number of idle cycles. Bit 15 14 Bit Name IDLS3 IDLS2 Initial Value 1 1 R/W R/W R/W Bit 7 6 ...