R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 557
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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12.10.12 Conflict between TCNT Write and Overflow/Underflow
If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 12.54 shows the operation timing when there is conflict between TCNT write and
overflow.
12.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
12.10.14 Interrupts and Module Stop State
If module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be
disabled before entering module stop state.
Figure 12.54 Conflict between TCNT Write and Overflow
Pφ
Address
Write
TCNT
TCFV flag
H'FFFF
TGR write cycle
T
TCNT address
1
T
2
Rev. 2.00 Sep. 16, 2009 Page 527 of 1036
Section 12 16-Bit Timer Pulse Unit (TPU)
M
TCNT write data
REJ09B0414-0200
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