R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 823
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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22.7.2
The programming/erasing interface parameters specify the operating frequency, storage place for
program data, start address of programming destination, and erase block number, and exchanges
the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the
on-chip RAM area. The initial values of programming/erasing interface parameters are undefined
at a reset or a transition to software standby mode.
Since registers of the CPU except for ER0 and ER1 are saved in the stack area during download of
an on-chip program, initialization, programming, or erasing, allocate the stack area before
performing these operations (the maximum stack size is 128 bytes). The return value of the
processing result is written in R0L. The programming/erasing interface parameters are used in
download control, initialization before programming or erasing, programming, and erasing. Table
22.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and
fail result parameter (FPFR) varies in initialization, programming, and erasure.
Table 22.4 Parameters and Target Modes
Note:
Download Control: The on-chip program is automatically downloaded by setting the SCO bit in
FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-Kbyte area starting
from the start address specified by FTDAR. Download is set by the programming/erasing interface
registers, and the download pass and fail result parameter (DPFR) indicates the return value.
Parameter
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
*
Programming/Erasing Interface Parameters
A single byte of the start address of the on-chip RAM specified by FTDAR
Download
O
O
Initialization
O
O
O
O
O
Programming
Erasure
O
O
Rev. 2.00 Sep. 16, 2009 Page 793 of 1036
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Section 22 Flash Memory
REJ09B0414-0200
Allocation
On-chip RAM*
R0L of CPU
ER0 of CPU
ER1 of CPU
ER0 of CPU
ER0 of CPU
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