R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 222
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Section 8 Bus Controller (BSC)
(4)
(a)
The number of access cycles in the basic bus interface can be specified as two or three cycles by
the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area
specified as 3-state access is specified as 3-state access space.
For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a
program wait (0 to 7 cycles) specified by WTCRA and WTCRB or an external wait by WAIT can
be inserted.
Assertion period of the chip select signal can be extended by CSACR.
(b) Byte Control SRAM Interface
The number of access cycles in the byte control SRAM interface is the same as that in the basic
bus interface.
(c)
The number of access cycles at full access in the burst ROM interface is the same as that in the
basic bus interface. The number of access cycles in the burst access can be specified as one to
eight cycles by the BSTS bit in BROMCR.
Rev. 2.00 Sep. 16, 2009 Page 192 of 1036
REJ09B0414-0200
Number of Access Cycles
Basic Bus Interface
Burst ROM Interface
Number of access cycles in the basic bus interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
Number of access cycles in byte control SRAM interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
Number of access cycles in the burst ROM interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+ number of external wait cycles by the WAIT pin]
+ number of CS extension cycles (0, 1, 2)
[+ number of external wait cycles by the WAIT pin]
+ number of CS extension cycles (0, 1)
[+number of external wait cycles by the WAIT pin]
+ number of burst access cycles (1 to 8) × number of burst accesses (0 to 63)
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