R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 1066
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Reset ......................................................... 88
Reset state................................................. 68
Resolution............................................... 730
S
Sample-and-hold circuit ......................... 727
Scan mode .............................................. 725
Serial communication interface (SCI) .... 601
Short address mode................................. 350
Single address mode ............................... 287
Single mode ............................................ 723
Slave receive mode................................. 705
Slave transmit mode ............................... 702
Sleep instruction ....................................... 98
Sleep mode ..................................... 882, 902
Smart card interface................................ 662
Software protection................................. 831
Software standby mode .................. 882, 904
Space state .............................................. 637
Stack status after exception handling...... 100
Standard serial communication interface
specifications for boot mode................... 837
Start bit ................................................... 637
State transitions ........................................ 68
Stop bit ................................................... 637
Strobe assert/negate timing..................... 193
Synchronous clearing ............................. 486
Synchronous operation ........................... 486
Synchronous presetting........................... 486
System clock (Iφ)............................ 181, 869
T
Toggle output.......................................... 483
Rev. 2.00 Sep. 16, 2009 Page 1036 of 1036
REJ09B0414-0200
Trace exception handling.......................... 92
Transfer information ............................... 350
Transfer information read
skip function ........................................... 359
Transfer information writeback
skip function ........................................... 360
Transfer modes ....................................... 290
Transmit/receive data.............................. 637
Trap instruction exception handling ......... 97
U
User boot MAT....................................... 781
User boot mode............................... 779, 820
User break controller (UBC)................... 143
User MAT............................................... 781
User program mode ........................ 779, 810
V
Vector table address.................................. 86
Vector table address offset........................ 86
W
Wait control ............................................ 209
Watchdog timer (WDT).......................... 589
Watchdog timer mode............................. 594
Waveform output by compare match...... 482
Write data buffer function....................... 252
Write data buffer function for
external data bus ..................................... 252
Write data buffer function for
peripheral modules.................................. 253
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