R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 13
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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4.4
4.5
4.6
4.7
Section 5 Exception Handling .............................................................................85
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Section 6 Interrupt Controller ............................................................................103
6.1
6.2
6.3
4.3.1
4.3.2
Pin Reset ............................................................................................................................. 83
Deep Software Standby Reset............................................................................................. 83
Watchdog Timer Reset ....................................................................................................... 83
Determination of Reset Generation Source......................................................................... 83
Exception Handling Types and Priority.............................................................................. 85
Exception Sources and Exception Handling Vector Table ................................................. 86
Reset ................................................................................................................................... 88
5.3.1
5.3.2
5.3.3
Traces.................................................................................................................................. 92
Address Error...................................................................................................................... 93
5.5.1
5.5.2
Interrupts............................................................................................................................. 95
5.6.1
5.6.2
Instruction Exception Handling .......................................................................................... 97
5.7.1
5.7.2
5.7.3
Stack Status after Exception Handling.............................................................................. 100
Usage Note........................................................................................................................ 101
Features............................................................................................................................. 103
Input/Output Pins.............................................................................................................. 105
Register Descriptions........................................................................................................ 105
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Interrupt Priority Registers A to I, K, L, P to R
(IPRA to IPRI, IPRK, IPRL, IPRP to IPRR) .................................................... 109
Reset Status Register (RSTSR)........................................................................... 81
Reset Control/Status Register (RSTCSR)........................................................... 82
Reset Exception Handling................................................................................... 89
Interrupts after Reset........................................................................................... 89
On-Chip Peripheral Functions after Reset Release ............................................. 90
Address Error Source.......................................................................................... 93
Address Error Exception Handling ..................................................................... 94
Interrupt Sources................................................................................................. 95
Interrupt Exception Handling ............................................................................. 96
Trap Instruction................................................................................................... 97
Sleep Instruction ................................................................................................. 98
Illegal Instruction................................................................................................ 99
Interrupt Control Register (INTCR) ................................................................. 106
CPU Priority Control Register (CPUPCR) ....................................................... 107
IRQ Enable Register (IER) ............................................................................... 111
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 113
IRQ Status Register (ISR)................................................................................. 118
Software Standby Release IRQ Enable Register (SSIER) ................................ 119
Rev. 2.00 Sep. 16, 2009 Page xi of xxviii
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