R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 356
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Section 9 DMA Controller (DMAC)
(4)
Figure 9.37 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the single cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Rev. 2.00 Sep. 16, 2009 Page 326 of 1036
REJ09B0414-0200
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the single cycle.
Activation Timing by DREQ Low Level
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Bφ
DREQ
Address bus
DACK
DMA
operation
Channel
Figure 9.37 Example of Transfer in Single Address Mode Activated
Wait
[1]
Request
Min. of 3 cycles
released
[2]
Bus
Duration of transfer
request disabled
Single
by DREQ Low Level
[3]
Transfer destination
Transfer source/
DMA single
Wait
cycle
Transfer request
enable resumed
[4]
Request
Min. of 3 cycles
[5]
released
Bus
Duration of transfer
request disabled
Single
[6]
Transfer destination
Transfer source/
DMA single
cycle
Wait
Transfer request
enable resumed
[7]
released
Bus
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