R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 157
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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6.6
The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt
control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt
control mode is selected by INTCR. Table 6.3 shows the differences between interrupt control
mode 0 and interrupt control mode 2.
Table 6.3
6.6.1
In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of
the CPU. Figure 6.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the
2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If
3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the
4. When the CPU accepts the interrupt request, it starts interrupt exception handling after
5. The PC and CCR contents are saved to the stack area during the interrupt exception handling.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Interrupt
Control
Mode
0
2
interrupt request is sent to the interrupt controller.
the I bit is cleared to 0, an interrupt request is accepted.
highest priority, sends the request to the CPU, and holds other interrupt requests pending.
execution of the current instruction has been completed.
The PC contents saved on the stack is the address of the first instruction to be executed after
returning from the interrupt handling routine.
Interrupt Control Modes and Interrupt Operation
Interrupt Control Mode 0
Interrupt Control Modes
Priority
Setting
Register
Default
IPR
Interrupt
Mask Bit
I
I2 to I0
Description
The priority levels of the interrupt sources are fixed
default settings.
The interrupts except for NMI is masked by the I bit.
Eight priority levels can be set for interrupt sources
except for NMI with IPR.
8-level interrupt mask control is performed by bits I2 to
I0.
Rev. 2.00 Sep. 16, 2009 Page 127 of 1036
Section 6 Interrupt Controller
REJ09B0414-0200
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