M3062LFGPFP#U5C Renesas Electronics America, M3062LFGPFP#U5C Datasheet - Page 263

• Manufacturer Part Number: M3062LFGPFP#U5C
• Description: IC M16C/62P MCU FLASH 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M3062LFGPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
18.1.5
Table 18.6
NOTES:
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pins to be
Given Priority when A/D
Converted
Reading of Result of A/D
Converter
1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if
In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code.
Table 18.6 shows the Repeat Sweep Mode 1 Specifications. Figure 18.9 shows the ADCON0 Register and
ADCON1 Register (Repeat Sweep Mode 1).
VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
Jan 10, 2006
Repeat Sweep Mode 1
Item
Repeat Sweep Mode 1 Specifications
Page 246 of 390
The input voltages on all pins selected by the ADGSEL1 to ADGSEL0 bits in the
ADCON2 register are A/D converted repeatedly, with priority given to pins
selected by the SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1
to ADGSEL0 bits.
Example : If AN0 selected, input voltages are A/D converted in order of
• When the TRG bit in the ADCON0 register is “0” (software trigger)
• When the TRG bit is “1” (ADTRG trigger)
Set the ADST bit to “0” (A/D conversion halted)
None generated
Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),
AN0 to AN3 (4 pins)
Read one of the AD0 to AD7 registers that corresponds to the selected pin
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
AN0 → AN1 → AN0 → AN2 → AN0 → AN3, and so on.
(1)
Specification
18. A/D Converter