M30626FJPFP#U5C Renesas Electronics America, M30626FJPFP#U5C Datasheet - Page 33
Manufacturer Part Number
IC M16C MCU FLASH 512K 100QFP
Renesas Electronics America
Specifications of M30626FJPFP#U5C
I²C, IEBus, UART/USART
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
A/D 26x10b; D/A 2x8b
-20°C ~ 85°C
Package / Case
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
M16C/62P Group (M16C/62P, M16C/62PT)
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
Jan 10, 2006
Page 31 of 96
2. Central Processing Unit (CPU)