HD64F7045F28V Renesas Electronics America, HD64F7045F28V Datasheet - Page 376

IC SH2 MCU FLASH 144QFP

HD64F7045F28V

Manufacturer Part Number
HD64F7045F28V
Description
IC SH2 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD64F7045F28V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7045F28V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7045F28V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 6 Instruction Descriptions
6.3.15
Description: Takes the OR of the top word of the Sx operand and the top word of the Sy operand,
stores the result in the top word of the Dz operand, and clears the bottom word of Dz with zeros.
When Dz is a register that has guard bits, the guard bits are also zeroed. When conditions are
specified for DCT and DCF, the instruction is executed when those conditions are TRUE. When
they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Note: The bottom word of the destination register and the guard bits are ignored when the DC bit
Rev. 5.00 Jun 30, 2004 page 360 of 512
REJ09B0171-0500O
Format
POR
Sx,Sy,Dz
DCT POR
Sx,Sy,Dz
DCF POR
Sx,Sy,Dz
is updated.
[if cc] POR (Logical OR): DSP Logical Operation Instruction
Abstract
Sx | Sy Dz, clear LSW of
Dz
If DC = 1, Sx | Sy Dz,
clear LSW of Dz; if 0, nop
If DC = 0, Sx | Sy Dz,
clear LSW of Dz; if 1, nop
111110**********
10110101xxyyzzzz
111110**********
10110110xxyyzzzz
111110**********
10110111xxyyzzzz
Code
1
1
1
Cycle
DC Bit
Update
SH-1
Instructions
Applicable
SH-2
SH-
DSP

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